公开(公告)号：US20120008377A1

公开(公告)日：2012-01-12

申请号：US12985289

申请日：2011-01-05

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C11/40 ,  G11C5/14

CPC classification number: G11C11/419

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract translation: 一种具有数据控制电源的静态随机存取存储器，其包括存储单元电路和至少一个写辅助电路，用于根据要写入存储单元电路的数据向存储单元电路供电。

公开(公告)号：US07973564B1

公开(公告)日：2011-07-05

申请号：US12874584

申请日：2010-09-02

Applicant: Ching-Te Chuang ,  Chien-Yu Lu

Inventor： Ching-Te Chuang ,  Chien-Yu Lu

IPC: H03K19/094

CPC classification number: H03K17/04123

Abstract: A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.

Abstract translation: 公开了一种高负载驱动装置。 驱动装置包括接收数字电压的逆变器。 逆变器反转数字电压，然后发出。 反相器的输出端子耦合到电容器，第一P型场效应晶体管（FET），第二P型FET，第一N型FET和第三N型FET。 上推电路由这些晶体管和第二N型FET组成并耦合到P型上推FET。 负载通过P型上推FET耦合到高电压。 当数字电压从低电平上升到高电平时，上推电路利用电容器的原始电压降来控制P型上推FET，由此P型上推电压的栅极电压 FET处于低于地电位的低稳定电压。 然后，负载被快速驱动。

公开(公告)号：US20150162077A1

公开(公告)日：2015-06-11

申请号：US14200040

申请日：2014-03-07

Applicant: Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

Inventor： Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/413

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract translation: 提供静态存储单元。 静态存储单元包括数据锁存电路和电压提供器。 数据锁存电路被配置为存储位数据。 数据锁存电路具有第一反相器和第二反相器，并且第一反相器和第二反相器彼此耦合。 第一反相器和第二反相器分别接收第一电压和第二电压作为电源电压。 电压提供器向数据锁存电路提供第一电压和第二电压。 当位数据被写入数据锁存电路时，电压提供器根据位数据调节第一和第二电压之一的电压值。

公开(公告)号：US08320164B2

公开(公告)日：2012-11-27

申请号：US12985289

申请日：2011-01-05

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C11/00

CPC classification number: G11C11/419

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract translation: 一种具有数据控制电源的静态随机存取存储器，其包括存储单元电路和至少一个写辅助电路，用于根据要写入存储单元电路的数据向存储单元电路供电。

公开(公告)号：US08385149B2

公开(公告)日：2013-02-26

申请号：US13075682

申请日：2011-03-30

Applicant: Hao-I Yang ,  Ching-Te Chuang ,  Wei Hwang

Inventor： Hao-I Yang ,  Ching-Te Chuang ,  Wei Hwang

IPC: G11C5/14

CPC classification number: G11C11/417

Abstract: The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

Abstract translation: 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

公开(公告)号：US08345504B2

公开(公告)日：2013-01-01

申请号：US13009240

申请日：2011-01-19

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

IPC: G11C11/40

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract translation: 提供具有多个单元的随机存取存储器（RAM）。 在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。 每个电池有两个逆变器; 电源控制器有两个电源开关。 对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

公开(公告)号：US08169814B2

公开(公告)日：2012-05-01

申请号：US12876582

申请日：2010-09-07

Applicant: Ching-Te Chuang ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

Inventor： Ching-Te Chuang ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L29/785

Abstract: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.

Abstract translation: 本发明提供了一种基于施密特触发器的FinFET静态随机存取存储器（SRAM）单元，其是8-FinFET结构。 FinFET具有两个独立门的功能。 与之前的工作中的10-FinFET结构相比，新的SRAM单元仅使用8个FinFET。 结果，本发明的电池结构可以节省芯片面积并且提高芯片密度。 此外，这种新的SRAM单元可以有效地解决6T SRAM单元在低工作电压下可能具有读出错误的常规问题。

公开(公告)号：US07952422B2

公开(公告)日：2011-05-31

申请号：US12511658

申请日：2009-07-29

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

IPC: H03K3/01

CPC classification number: G11C5/147 ,  G11C11/412 ,  G11C11/417

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract translation: 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

公开(公告)号：US07787285B2

公开(公告)日：2010-08-31

申请号：US12140366

申请日：2008-06-17

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

Abstract translation: 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 在对应的一个字线结构的控制下，每个非对称单元可以选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

公开(公告)号：US07782092B2

公开(公告)日：2010-08-24

申请号：US11762257

申请日：2007-06-13

Applicant: Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

Inventor： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC: H03K19/094

CPC classification number: G01R31/31725

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract translation: 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。