-
公开(公告)号：US11658623B2
公开(公告)日：2023-05-23
申请号：US17378861
申请日：2021-07-19
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03F3/2173 , H04R3/00 , H04R29/001 , H03F3/185 , H03F2200/03 , H03F2200/165 , H03F2200/168 , H03F2200/267 , H04R2499/11
Abstract: The present disclosure relates to Class D amplifier circuitry comprising a mode controller configured to dynamically adjust an operational switching mode of the Class D amplifier over a range between a Class AD mode and a Class BD mode.
-
公开(公告)号：US10461714B2
公开(公告)日：2019-10-29
申请号：US15886103
申请日：2018-02-01
Inventor： John Paul Lesso , Toru Ido
Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
-
公开(公告)号：US09628040B2
公开(公告)日：2017-04-18
申请号：US14836006
申请日：2015-08-26
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
-
公开(公告)号：US20170019079A1
公开(公告)日：2017-01-19
申请号：US15278862
申请日：2016-09-28
Inventor： John P. Lesso , Toru Ido
CPC classification number: H03F3/2171 , H03F1/0211 , H03F3/187 , H03F3/217 , H03F2200/165 , H03F2200/171 , H03F2200/333 , H03F2200/351 , H03G1/0088
Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.
Abstract translation: 具有提高功率效率的D类放大器电路的方法和装置。 电路具有至少具有第一和第二开关的输出级和接收要被放大的输入信号SIN和第一时钟信号fSW的调制器。 调制器基于输入信号在开关周期内控制第一和第二开关的占空比，其中开关周期具有基于第一时钟信号的开关频率。 频率控制器响应于输入信号的幅度的指示来控制第一时钟信号的频率，以便提供第一输入信号幅度的第一开关频率和在第二输入信号幅度下的第二，较低开关频率 ，输入信号幅度。 在低信号幅度下可以容忍较低的开关频率，并且以这种方式改变开关频率，从而在降低开关功率损耗的同时保持稳定性。
-
公开(公告)号：US12253487B2
公开(公告)日：2025-03-18
申请号：US18685979
申请日：2022-08-25
Inventor： John Paul Lesso , Toru Ido
IPC: G01N27/327 , G01R19/165
Abstract: Circuitry for and methods of analyte measurement Circuitry for measuring a characteristic of an electrochemical cell, the circuitry comprising: a hysteretic comparator having a first comparator input, a second comparator input and a comparator output; a feedback path between the comparator output and the second comparator input configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate the feedback signal, wherein the loop filter comprises the electrochemical cell.
-
Patent Agency Ranking
公开(公告)号：US12142259B2
公开(公告)日：2024-11-12
申请号：US18318269
申请日：2023-05-16
Inventor： John Paul Lesso , Toru Ido
Abstract: A method of detecting live speech comprises: receiving a signal containing speech; obtaining a first component of the received signal in a first frequency band, wherein the first frequency band includes audio frequencies; and obtaining a second component of the received signal in a second frequency band higher than the first frequency band. Then, modulation of the first component of the received signal is detected; modulation of the second component of the received signal is detected; and the modulation of the first component of the received signal and the modulation of the second component of the received signal are compared. It may then be determined that the speech may not be live speech, if the modulation of the first component of the received signal differs from the modulation of the second component of the received signal.
-
公开(公告)号：US11998948B2
公开(公告)日：2024-06-04
申请号：US16921369
申请日：2020-07-06
Inventor： John Paul Lesso , Toru Ido
IPC: B06B1/02
CPC classification number: B06B1/0261 , B06B2201/55
Abstract: The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: a power supply; a reservoir capacitance; switch network circuitry; and control circuitry. The control circuitry is configured to control operation of the switch network circuitry so as to charge the reservoir capacitance from the power supply and to transfer charge between the reservoir capacitance and the piezoelectric transducer.
-
公开(公告)号：US11804813B2
公开(公告)日：2023-10-31
申请号：US17386287
申请日：2021-07-27
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2175 , H03G7/002 , H03G7/007 , H03F3/2171 , H03F3/2173 , H03F2200/102 , H03F2200/339 , H03F2200/432
Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.
-
公开(公告)号：US10826478B2
公开(公告)日：2020-11-03
申请号：US16735297
申请日：2020-01-06
Inventor： Toru Ido
Abstract: This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (PWidth) and to output a PWM signal (SPWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.
-
公开(公告)号：US10432151B2
公开(公告)日：2019-10-01
申请号：US15988823
申请日：2018-05-24
Inventor： John Paul Lesso , Toru Ido
IPC: H03F3/68 , H04B15/00 , H04R3/02 , H03F1/32 , H03F3/187 , H04R3/04 , H03F1/02 , H03F3/217 , H04R1/10
Abstract: This application relates to methods and apparatus for amplification of audio signals with improved audio performance. An audio driving circuit has an amplifier module in a forward signal path between an input for receiving an input audio signal (SIN) and an output for outputting an audio driving signal (VOUT). A pre-distortion module is operable to apply a first transfer function to the signal in the forward signal path upstream of the amplifier module, wherein the first transfer function comprises a non-linear distortion function based on at least one distortion setting. An error block is arranged to receive a first signal (SFF) derived from the input signal and a second signal (SFB) indicative of the voltage of the audio driving signal and determine a first error signal (ε1) indicative of a difference between the first and second signals. The pre-distortion module is operable to control the distortion setting(s) based on the first error signal.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.031 seconds)
