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    Electronic circuit for implementing a permutation operation
    3.
    发明申请
    Electronic circuit for implementing a permutation operation 失效
    用于实现置换操作的电子电路

    公开(公告)号：US20070011220A1

    公开(公告)日：2007-01-11

    申请号：US11390791

    申请日：2006-03-28

    申请人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Mevergnies ,  Hans-Werner Tast

    发明人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Mevergnies ,  Hans-Werner Tast

    IPC分类号： G06F17/15

    CPC分类号： G06F7/766

    摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.

    摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。

    Electronic circuit for implementing a permutation operation
    4.
    发明授权
    Electronic circuit for implementing a permutation operation 失效
    用于实现置换操作的电子电路

    公开(公告)号：US07783690B2

    公开(公告)日：2010-08-24

    申请号：US11390791

    申请日：2006-03-28

    申请人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Neve de Mevergnies ,  Hans-Werner Tast

    发明人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Neve de Mevergnies ,  Hans-Werner Tast

    IPC分类号： G06F15/00

    CPC分类号： G06F7/766

    摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.

    摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。

    Embedding of dynamic circuits in a static environment
    5.
    发明授权
    Embedding of dynamic circuits in a static environment 失效
    在静态环境中嵌入动态电路

    公开(公告)号：US06518793B2

    公开(公告)日：2003-02-11

    申请号：US09815355

    申请日：2001-03-22

    申请人： Jens Leenstra ,  Hans-Werner Tast ,  Dieter Wendel ,  Peter Hofstee

    发明人： Jens Leenstra ,  Hans-Werner Tast ,  Dieter Wendel ,  Peter Hofstee

    IPC分类号： H03K1900

    CPC分类号： G01R31/318577 ,  G01R31/318583 ,  G01R31/318586

    摘要： The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

    摘要翻译： 本发明涉及关于逻辑和定时验证的改进，作为包括在静态环境中嵌入动态逻辑电路的硬件电路的可测试性。 包含动态逻辑电路的时钟宏在锁存器的输入和输出两端都被限制，保持输入和输出信号到时钟宏。 静态输入信号用波形格式化装置处理，以产生可用于动态逻辑电路的评估的波形，并且动态逻辑输出信号通过设置/复位锁存器转换回静态信号，使得它可以 被静态嵌入电路的时钟信号锁存。 因此，芯片设计中的定时和逻辑仿真分析方法可以与静态逻辑中使用的分析方法相同，特别是可以使用LSSD测试方法。

    MANAGING TRANSACTIONAL AND NON-TRANSACTIONAL STORE OBSERVABILITY
    7.
    发明申请
    MANAGING TRANSACTIONAL AND NON-TRANSACTIONAL STORE OBSERVABILITY 有权
    管理交易和非交易商店的可观察性

    公开(公告)号：US20130339615A1

    公开(公告)日：2013-12-19

    申请号：US13524386

    申请日：2012-06-15

    申请人： Khary J. Alexander ,  Christian Jacobi ,  Hans-Werner Tast ,  Patrick M. West

    发明人： Khary J. Alexander ,  Christian Jacobi ,  Hans-Werner Tast ,  Patrick M. West

    IPC分类号： G06F12/08

    CPC分类号： G06F12/084 ,  G06F9/467 ,  G06F11/1474 ,  G06F12/0828

    摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.

    摘要翻译： 实施例涉及控制事务和非交易存储的可观察性。 一方面包括接收一个或多个存储指令。 一个或多个存储指令在活动事务中启动并且包括存储数据。 活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。 存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。 接收到有效事务终止的信号。 如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。

    METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT
    8.
    发明申请
    METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT 失效
    验证多处理器环境的实现的相似算法的方法

    公开(公告)号：US20100146210A1

    公开(公告)日：2010-06-10

    申请号：US12328242

    申请日：2008-12-04

    申请人： CHRISTIAN HABERMANN ,  Ralf Winkelmann ,  Hans-Werner Tast ,  Christian Jacobi

    发明人： CHRISTIAN HABERMANN ,  Ralf Winkelmann ,  Hans-Werner Tast ,  Christian Jacobi

    IPC分类号： G06F12/08 ,  G06G7/62

    CPC分类号： G06F12/0815

    摘要： A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of: generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events, wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further a single processor model and a computer program product to execute said method are described.

    摘要翻译： 描述了在单个处理器模型上验证多处理器环境的实现的一致性算法的方法，包括以下步骤：生成反映多处理器环境内的单个处理器的专用高速缓存层级的参考模型，以刺激专用高速缓存层级 具有来自核心侧和/或来自嵌套侧的模拟请求和/或交叉无效，基于接口事件设置两个构建日期和两个到期日期，扩充专用高速缓存层级中可用的所有数据，其中多处理器一致性不是 观察缓存层次结构是否已将数据返回给处理器，其过期日期早于之前使用的所有数据的最新构建日期。 此外，描述了执行所述方法的单个处理器模型和计算机程序产品。

    Methods of Cache Bounded Reference Counting
    9.
    发明申请
    Methods of Cache Bounded Reference Counting 失效
    缓存边界引用计数方法

    公开(公告)号：US20100030968A1

    公开(公告)日：2010-02-04

    申请号：US12184165

    申请日：2008-07-31

    申请人： Eberhard Pasch ,  Hans-Werner Tast ,  Achim Haessler ,  Markus Nosse ,  Elmar Zipp

    发明人： Eberhard Pasch ,  Hans-Werner Tast ,  Achim Haessler ,  Markus Nosse ,  Elmar Zipp

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0261 ,  G06F12/0802

    摘要： A computer implemented method of cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object “Z” initially stored in an object “O” is fetched and the cache hardware is queried whether the reference to the object “Z” is a valid reference, is in the cache, and has a continuity flag set to “on”. If so, the object “O” is locked for an update, a reference counter is decremented for the object “Z” if the object “Z” resides in the cache, and a return code is set to zero to indicate that the object “Z” is de-referenced and that its storage memory can be released and re-used if the reference counter for the object “Z” reaches zero. Thereafter, the cache hardware is similarly queried regarding an object “N” that will become a new reference of object “O”.

    摘要翻译： 具有自动存储器管理的计算机语言的高速缓存有界引用计数的计算机实现方法，其中例如对最初存储在对象“O”中的对象“Z”的引用被查询，并且查询高速缓存硬件是否被引用 对象“Z”是有效的引用，位于缓存中，并具有设置为“开”的连续性标志。 如果是这样，对象“O”被锁定以进行更新，如果对象“Z”驻留在高速缓存中，对象“Z”的引用计数器递减，并且将返回码设置为零以指示对象“ Z“被取消引用，并且如果对象”Z“的引用计数器达到零，则可以将其存储器释放并重新使用。 此后，对于将成为对象“O”的新引用的对象“N”，类似地查询高速缓存硬件。

    Checkpointing a superscalar, out-of-order processor for error recovery
    10.
    发明授权
    Checkpointing a superscalar, out-of-order processor for error recovery 有权
    检查一个超标量，无序处理器进行错误恢复

    公开(公告)号：US06968476B2

    公开(公告)日：2005-11-22

    申请号：US10180385

    申请日：2002-06-26

    申请人： Harry Stefan Barowski ,  Hartmut Schwermer ,  Hans-Werner Tast

    发明人： Harry Stefan Barowski ,  Hartmut Schwermer ,  Hans-Werner Tast

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38 ,  G06F11/14 ,  G06F11/00

    CPC分类号： G06F9/3842 ,  G06F9/30174 ,  G06F9/3834 ,  G06F9/3863 ,  G06F9/3885

    摘要： The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)(60) for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)(64) with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions. Handshake synchronization for consistent updates between storage in an L2-cache (66) via a Store Buffer (65) and an Architected Register Array (ARA) (64) is provided which is based on the youngest instruction ID (40) stored in the Checkpoint State Buffer (CSB) (60).

    摘要翻译： 本发明涉及从给定检查点内置错误恢复的数据处理系统。 为了对每个周期的多于一个指令进行检查，建议收集用于检查点状态的缓冲器（CSB）（60）中的相应多个CISC / RISC指令执行的预定最大数量的寄存器内容的更新，由此检查点 状态包括与所述多个CISC指令相对应的寄存器可更新的缓冲器槽，以及与所述多个最小外部指令相关联的程序计数器值的条目，并且以新鲜的方式更新建筑物寄存器阵列（ARA）（64） 在完成所述多个外部指令的所述最小外部指令之后确定在所述寄存器数据中没有检测到错误之后，收集的寄存器数据。 提供握手同步，用于通过存储缓冲器（65）和架构化寄存器阵列（ARA）（64）存储在L2高速缓存（66）中的一致更新，其基于存储在检查点中的最年轻的指令ID（40） 状态缓冲区（CSB）（60）。