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260 条记录 (耗时 0.026 秒)

    Single-ended semiconductor receiver with built in threshold voltage difference
    1.
    发明授权
    Single-ended semiconductor receiver with built in threshold voltage difference 失效
    单端半导体接收器内置阈值电压差

    公开(公告)号：US06222395B1

    公开(公告)日：2001-04-24

    申请号：US09225112

    申请日：1999-01-04

    申请人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G05F110

    CPC分类号： G05F3/205

    摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

    摘要翻译： 一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。 阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。 也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。 也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。

    High frequency valid data strobe
    2.
    发明授权
    High frequency valid data strobe 失效
    高频有效数据选通

    公开(公告)号：US06177807B1

    公开(公告)日：2001-01-23

    申请号：US09322465

    申请日：1999-05-28

    申请人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G03K1716

    CPC分类号： G06F13/4086 ,  H03K5/06 ,  H04L25/0298

    摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

    摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控​​制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

    Very low power logic circuit family with enhanced noise immunity
    3.
    发明授权
    Very low power logic circuit family with enhanced noise immunity 有权
    超低功耗逻辑电路系列，具有增强的抗噪声能力

    公开(公告)号：US6111425A

    公开(公告)日：2000-08-29

    申请号：US173436

    申请日：1998-10-15

    申请人： Claude L. Bertin ,  Russell J. Houghton ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： Claude L. Bertin ,  Russell J. Houghton ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： H03K19/003 ,  H03K3/356 ,  H03K19/173 ,  H03K17/16

    CPC分类号： H03K3/356113 ,  H03K19/1738

    摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.

    摘要翻译： 一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。 在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。 本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。 在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。 第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

    Methods and apparatus for blowing and sensing antifuses
    5.
    发明授权
    Methods and apparatus for blowing and sensing antifuses 失效
    用于吹制和检测反熔丝的方法和装置

    公开(公告)号：US06346846B1

    公开(公告)日：2002-02-12

    申请号：US09466479

    申请日：1999-12-17

    申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  William R. Tonti ,  Nicholas M. Van Heel

    发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  William R. Tonti ,  Nicholas M. Van Heel

    IPC分类号： H01H3776

    CPC分类号： G11C5/145 ,  G11C17/18

    摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.

    摘要翻译： 提供了用于吹制和检测反熔丝的方法和装置。 具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。 在第二和第三方面中，提供了用于执行第一方面的方法的装置。 在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压， 第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。 在第五方面中，提供了用于执行第四方面的方法的装置。

    Capacitive precharging and discharging network for converting N bit input into M bit output
    6.
    发明授权
    Capacitive precharging and discharging network for converting N bit input into M bit output 失效
    用于将N位输入转换为M位输出的电容式预充放电网络

    公开(公告)号：US06195027B1

    公开(公告)日：2001-02-27

    申请号：US09302744

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  Steven W. Tomashot ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  Steven W. Tomashot ,  William R. Tonti

    IPC分类号： H03M720

    CPC分类号： G11C8/10

    摘要： A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

    摘要翻译： 提供了用于将n个输入信号及其与m个输出信号之一的补码进行解码的方法和结构。 提供具有m个输出节点的电容网络。 输出节点预充电到给定的电压值。 提供N个输入信号及其补码，每个具有高值或低值。 响应于输入信号的真值和补码值的给定输入模式，至少一个但不到所有输出节点的输出模式被放电到小于给定电压但大于输出模式的输出值的值。 放电节点的输出模式是为任何给定模式的输入信号提供一个且仅一个放电或一个且仅一个未充电节点。 优选地，电容网络包括NMOS反转电容器。

    Multi-level storage gain cell with stepline
    7.
    发明授权
    Multi-level storage gain cell with stepline 失效
    带梯级的多级存储增益单元

    公开(公告)号：US5761114A

    公开(公告)日：1998-06-02

    申请号：US803034

    申请日：1997-02-19

    申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    IPC分类号： G11C11/56

    CPC分类号： G11C11/565 ,  G11C16/30

    摘要： A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.

    摘要翻译： 示出了在增益单元中使用多电平信号的方法和装置。 该方法首先在增益单元中存储多电平信号的值。 然后，当增益单元的步进波形对应于存储在增益单元内的多电平信号的值时，增益单元输出导通信号。 最后，通过导通信号和步进波形的相应电平来确定多电平信号的值。 增益单元包括响应于从步进信号发生器产生的步进波形的输入装置，存储装置和电平比较器，并输出用于确定存储在存储装置中的多电平信号的值的导通信号。

    Method of forming connection and anti-fuse in layered substrate such as SOI
    8.
    发明授权
    Method of forming connection and anti-fuse in layered substrate such as SOI 有权
    在诸如SOI的层状衬底中形成连接和反熔丝的方法

    公开(公告)号：US07226816B2

    公开(公告)日：2007-06-05

    申请号：US11055106

    申请日：2005-02-11

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
    9.
    发明授权
    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效
    用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法

    公开(公告)号：US06436749B1

    公开(公告)日：2002-08-20

    申请号：US09658655

    申请日：2000-09-08

    申请人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    发明人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    IPC分类号： H01L218238

    CPC分类号： H01L27/092 ,  H01L21/823842

    摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.

    摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。