公开(公告)号：US12100763B2

公开(公告)日：2024-09-24

申请号：US17482840

申请日：2021-09-23

Applicant: DENSO CORPORATION

Inventor： Yasushi Urakami ,  Jun Saito ,  Yusuke Yamashita

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/1095

Abstract: A semiconductor device includes a cell section having a plurality of gate structures, and an outer peripheral section surrounding the cell section. The cell section includes a semiconductor substrate, the plurality of gate structures, a first electrode and a second electrode. The cell section and the outer peripheral section includes a protective film made of a material having a thermal conductivity lower than that of the first electrode. The protective film extends from the outer peripheral section to an outer edge portion of the cell section adjacent to the outer peripheral section and covers a portion of the first electrode adjacent to the outer peripheral section.

公开(公告)号：US10367091B2

公开(公告)日：2019-07-30

申请号：US16075840

申请日：2016-12-26

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yasushi Urakami

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/08 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417

Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.

公开(公告)号：US09911803B2

公开(公告)日：2018-03-06

申请号：US15023498

申请日：2014-09-22

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.

公开(公告)号：US09219142B2

公开(公告)日：2015-12-22

申请号：US14491332

申请日：2014-09-19

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region.

Abstract translation: 半导体器件包括具有元件区域和端接区域的半导体衬底。 元件区域包括具有第一导电类型的第一主体区域，具有第二导电类型的第一漂移区域和具有第一导电类型的第一浮动区域。 终止区域包括FLR区域，第二漂移区域和第二浮动区域。 FLR区域具有第一导电类型并且围绕元件区域。 第二漂移区域具有第二导电类型，与FLR区域接触并围绕FLR区域。 第二浮动区域具有第一导电类型并被第二漂移区域围绕。 第二浮动区域围绕元件区域。 第二浮动区域中的至少一个相对于元件区域中最近的一个FLR区域放置在元件区域侧。

公开(公告)号：US11004765B2

公开(公告)日：2021-05-11

申请号：US16667111

申请日：2019-10-29

Applicant: DENSO CORPORATION

Inventor： Jun Saito ,  Yusuke Yamashita ,  Yasushi Urakami

IPC: H01L29/78 ,  H01L23/367 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L23/373 ,  H01L29/739 ,  H01L29/49

Abstract: A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. A side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that passes through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface.

公开(公告)号：US11233147B2

公开(公告)日：2022-01-25

申请号：US16745682

申请日：2020-01-17

Applicant: DENSO CORPORATION

Inventor： Masato Noborio ,  Jun Saito ,  Yukihiko Watanabe

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.

公开(公告)号：US10374081B2

公开(公告)日：2019-08-06

申请号：US16075870

申请日：2016-12-26

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yasushi Urakami

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L21/04 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417

Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.

公开(公告)号：US12205984B2

公开(公告)日：2025-01-21

申请号：US17829791

申请日：2022-06-01

Applicant: DENSO CORPORATION

Inventor： Jun Saito ,  Keita Kataoka ,  Yusuke Yamashita ,  Yukihiko Watanabe ,  Katsuhiro Kutsuki ,  Youngshin Eum

IPC: H01L29/06 ,  H01L29/739

Abstract: A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.

公开(公告)号：US10964809B2

公开(公告)日：2021-03-30

申请号：US16816463

申请日：2020-03-12

Applicant: DENSO CORPORATION

Inventor： Masato Noborio ,  Masayasu Ishiko ,  Jun Saito

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device comprises: a cell region that includes a semiconductor element; an outer peripheral region that surrounds an outer periphery of the cell region; a substrate that has a front surface and a back surface, and is made of a semiconductor of a first or second conductivity type; a first conductivity layer that is formed on the front surface of the substrate and made of the semiconductor of the first conductivity type having a lower impurity concentration than impurity concentration of the substrate; a first electrode that is provided on an opposite side of the substrate across the first conductivity layer, the first electrode being provided in the semiconductor element; and a second electrode that is placed toward the back surface of the substrate, the second electrode being provided in the semiconductor element.

公开(公告)号：US10056374B2

公开(公告)日：2018-08-21

申请号：US15681822

申请日：2017-08-21

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Yasushi Urakami ,  Sachiko Aoi

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7813

Abstract: A switching device may be provided with: a semiconductor substrate; a trench provided in an upper surface of the semiconductor substrate; a gate insulating layer covering an inner surface of the trench; and a gate electrode located in the trench. The semiconductor substrate includes: a first semiconductor region being in contact with the gate insulating layer; a body region being in contact with the gate insulating layer under the first semiconductor region; a second semiconductor region being in contact with the gate insulating layer under the body region; a bottom region being in contact with the gate insulating layer at a bottom surface of the trench; and a connection region being in contact with the gate insulating layer at a lateral surface of the trench and connecting the body region and the bottom region. The connection region is thicker than the bottom region.