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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250118357A1

    公开(公告)日：2025-04-10

    申请号：US18892187

    申请日：2024-09-20

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sooji NAM ,  Sung Haeng CHO ,  Jeho NA ,  Chihun SUNG ,  Kyunghee CHOI ,  Jung Hoon HAN

    IPC: G11C11/4096 ,  H10B12/00

    Abstract: Provided is a semiconductor device including a substrate, a first transistor on the substrate, an interlayer insulating layer covering the first transistor, a second transistor on the interlayer insulating layer, and a storage node contact passing through the interlayer insulating layer, and connecting any one of source/drain electrodes of the first transistor and a gate electrode of the second transistor, wherein a first channel pattern of the first transistor may include an n-type oxide transistor, and a second channel pattern of the second transistor may include an p-type oxide transistor.

    SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR
    6.
    发明申请
    SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR 有权

    公开(公告)号：US20230102625A1

    公开(公告)日：2023-03-30

    申请号：US17529817

    申请日：2021-11-18

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Byung-Do YANG ,  Sooji NAM ,  Jaehyun MOON ,  Jae-Eun PI ,  Jae-Min KIM

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/417

    Abstract: Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.

    METHOD FOR FORMING THIN FILM TRANSISTOR
    7.
    发明申请
    METHOD FOR FORMING THIN FILM TRANSISTOR 有权

    公开(公告)号：US20250120159A1

    公开(公告)日：2025-04-10

    申请号：US18887701

    申请日：2024-09-17

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Chihun SUNG ,  Sooji NAM

    IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: Provided is a thin film transistor including a substrate, a channel layer on the substrate, a first source/drain electrode and a second source/drain electrode spaced apart on the substrate and on the channel layer in a first direction parallel to the substrate, a gate insulation layer on the substrate, the channel layer, the first source/drain electrode, and the second source/drain electrode, and a gate electrode on the gate insulation layer between the first and second source/drain electrodes, wherein the uppermost level of the gate electrode is substantially the same as the uppermost level of the gate insulation layer.

    CMOS LOGIC ELEMENT INCLUDING OXIDE SEMICONDUCTOR
    8.
    发明申请
    CMOS LOGIC ELEMENT INCLUDING OXIDE SEMICONDUCTOR 有权

    公开(公告)号：US20230097393A1

    公开(公告)日：2023-03-30

    申请号：US17520853

    申请日：2021-11-08

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Byung-Do YANG ,  Sooji NAM ,  Jaehyun MOON ,  Jae-Eun PI ,  Jae-Min KIM

    IPC: H01L27/092 ,  H01L29/24 ,  H03K19/0185 ,  H03K19/0948 ,  H01L27/02

    Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

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