公开(公告)号：US6071789A

公开(公告)日：2000-06-06

申请号：US190054

申请日：1998-11-10

申请人： Fu-Liang Yang ,  Erik S. Jeng ,  Bih-Tiao Lin ,  I-Ping Lee

发明人： Fu-Liang Yang ,  Erik S. Jeng ,  Bih-Tiao Lin ,  I-Ping Lee

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L28/60 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10897 ,  H01L28/55

摘要： A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.

摘要翻译： 一种用于在衬底上制造半导体器件的同时形成存储节点和多个互连的方法。 该方法包括以下步骤：在所述单元阵列区域和所述周边上形成第一介电层; 通过所述单元阵列区域和所述外围区域中的所述第一介电层形成多个第一接触孔，所述外围区域包括位线和字线，所述字线和所述位线用于寻址所述存储单元; 在所述多个第一接触孔和所述第一介电层上形成第一导电层; 图案化和蚀刻所述第一导电层以同时形成所述存储节点和所述多个互连; 随后在所述第一介电层，所述存储节点和所述多个互连上形成第二电介质层和第二导电层; 以及图案化和蚀刻所述第二介电层和所述第二导电层以形成电荷存储装置和多个接触插塞。

公开(公告)号：US06458706B1

公开(公告)日：2002-10-01

申请号：US09507903

申请日：2000-02-22

申请人： Eddy Chiang ,  Erik S. Jeng ,  I-Ping Lee ,  Kuei-Chuen Ho

发明人： Eddy Chiang ,  Erik S. Jeng ,  I-Ping Lee ,  Kuei-Chuen Ho

IPC分类号： H01L21302

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L27/10855 ,  H01L27/10888

摘要： A new method is provided to treat contact holes after hole formation has been completed. A layer of non-conformal dielectric is deposited over the surface in which the contact hole has been formed thereby including the sidewalls and bottom of the contact hole. The non-conformal dielectric will be unevenly deposited on The sidewalls and bottom of the contact hole. This results in a relatively light deposition of non-conformal dielectric along the lower portions of the sidewalls and on the bottom of the contact hole with a heavier coating of non-conformal dielectric being deposited along the upper reaches of the contact hole. The objective of the invention is to prevent the enlargement of the hole diameter during subsequent processing steps. The non-conformal dielectric can be removed from the bottom using a wet etch.

摘要翻译： 提供了一种新方法，用于在孔形成完成后处理接触孔。 在其上形成接触孔的表面上沉积一层非保形电介质，由此包括接触孔的侧壁和底部。 非共形电介质将不均匀地沉积在接触孔的侧壁和底部上。 这导致沿着侧壁的下部和接触孔的底部上的非保形电介质的相对轻的沉积，具有沿接触孔的上游层沉积的较重的非保形电介质涂层。 本发明的目的是在随后的处理步骤中防止孔直径的扩大。 可以使用湿蚀刻从底部去除非保形电介质。

公开(公告)号：US6057246A

公开(公告)日：2000-05-02

申请号：US67927

申请日：1998-04-28

申请人： I-Ping Lee ,  Erik S. Jeng ,  Chyei-Jer Hsieh

发明人： I-Ping Lee ,  Erik S. Jeng ,  Chyei-Jer Hsieh

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/32136

摘要： A method for etching a metal layer on a substrate with dimensional control is disclosed. First, an anti-reflection layer is formed over the metal layer. A photoresist layer is then formed over the anti-reflection layer. A metal layer pattern is defined by patterning the photoresist layer. An etching process is performed to etch the anti-reflection layer with dimensional loss compared with the metal layer pattern, by using the photoresist layer as a mask. Another etching process is performed to etch the metal layer with dimensional gain compared with the anti-reflection layer, by using the anti-reflection layer as a mask. A metal layer with nearly zero-biased dimension is achieved.

摘要翻译： 公开了一种用于在具有尺寸控制的基板上蚀刻金属层的方法。 首先，在金属层上形成防反射层。 然后在抗反射层上形成光致抗蚀剂层。 通过图案化光致抗蚀剂层来限定金属层图案。 通过使用光致抗蚀剂层作为掩模，执行蚀刻处理以与金属层图案相比尺寸损失来蚀刻抗反射层。 通过使用防反射层作为掩模，执行另一蚀刻处理以与抗反射层相比尺寸增益来蚀刻金属层。 实现了具有几乎零偏置尺寸的金属层。

公开(公告)号：US06376384B1

公开(公告)日：2002-04-23

申请号：US09557398

申请日：2000-04-24

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  I-Ping Lee ,  Eddy Chiang

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  I-Ping Lee ,  Eddy Chiang

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76897 ,  Y10S438/963

摘要： A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.

摘要翻译： 一种通过氧化硅层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的氮化硅层，其限定图案化氮化硅层下面的接触区域。 然后在图案化的氮化硅层上形成氧化硅层。 然后在使用包含氟碳化合物蚀刻剂气体的第一蚀刻剂气体组合物的反应离子蚀刻（RIE）方法的同时蚀刻氧化硅层，以形成：（1）蚀刻的氧化硅层，其暴露接触区域而基本上不蚀刻图案 氮化硅层; 和（2）在蚀刻的氧化硅层和图案化氮化硅层中的至少一个上形成的氟碳聚合物残渣层。 最后，使用包含碳氟化合物蚀刻剂气体和氧气的第二蚀刻剂气体组合物的下游等离子体蚀刻方法，从基底上剥离碳氟聚合物残余物层。 该方法通常也可用于在存在氮化硅层的情况下蚀刻氧化硅层。 类似地，该方法通常也可用于从包括但不限于氧化硅层和氮化硅层的集成电路层去除碳氟聚合物残余物层。

公开(公告)号：US5968711A

公开(公告)日：1999-10-19

申请号：US69376

申请日：1998-04-28

申请人： I-Ping Lee ,  Erik S. Jeng

发明人： I-Ping Lee ,  Erik S. Jeng

IPC分类号： H01L21/027 ,  H01L21/3213 ,  G03F7/36

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/32136

摘要： A new method of etching AlCu or AlSiCu lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A layer of AlCu or AlSiCu is deposited overlying insulating layer. A silicon nitride or titanium nitride/silicon dioxide layer is deposited overlying the metal layer wherein a hard mask is formed. The hard mask is covered with a layer of photoresist which is exposed to actinic light wherein the hard mask prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The AlCu or AlSiCu layer and the barrier layer not covered by the patterned hard mask are etched away to form metal lines having an outwardly tapered profile.

摘要翻译： 描述了蚀刻AlCu或AlSiCu线的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 一层AlCu或AlSiCu沉积在绝缘层上。 在其上形成硬掩模的金属层上沉积氮化硅或氮化钛/二氧化硅层。 硬掩模被暴露于光化光的光致抗蚀剂层覆盖，其中硬掩模防止光化反射光从其表面。 显影和图案化光致抗蚀剂层以形成所需的光致抗蚀剂掩模。 硬掩模被蚀刻掉，其未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 AlCu或AlSiCu层和未被图案化硬掩模覆盖的阻挡层被蚀刻掉以形成具有向外锥形轮廓的金属线。