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    Generation of graphical design representation from a design specification data file
    1.
    发明授权
    Generation of graphical design representation from a design specification data file 有权
    从设计规范数据文件生成图形设计表示

    公开(公告)号：US07412669B1

    公开(公告)日：2008-08-12

    申请号：US11483239

    申请日：2006-07-06

    申请人： Fung Fung Lee ,  Chukwuweta Chukwudebe

    发明人： Fung Fung Lee ,  Chukwuweta Chukwudebe

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045

    摘要： Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.

    摘要翻译： 描述了用于生成电子电路设计的框图的方法和装置。 在一个实施例中，识别多主母线，多主总线的总线主机，多主总线的总线从机，存储器，协处理器和输入/输出端口的每个实例。 输入/输出端口的实例围绕图的第一个区域的周边放置。 多主总线的每个实例被放置在第一区域内的总线区域中，并且每个总线主机被放置在主区域中。 总线的总线从站被收集在一组中，并且组被作为单个块放置在第一区域内的从属区域中。 总线从站的组与总线主站对齐。 输出与放置表示一致的图示表示。

    Integrated circuit with improved logic cells
    2.
    发明授权
    Integrated circuit with improved logic cells 有权
    具有改进的逻辑单元的集成电路

    公开(公告)号：US07719311B1

    公开(公告)日：2010-05-18

    申请号：US12469348

    申请日：2009-05-20

    申请人： Fung Fung Lee ,  Wen Zhou

    发明人： Fung Fung Lee ,  Wen Zhou

    IPC分类号： H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17728

    摘要： The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

    摘要翻译： 本发明提供具有改进的逻辑单元的集成电路。 在一个实施例中，提供了具有多个逻辑单元（LC）的集成电路，每个LC包括：具有LUT输出端的查找表; 和第一复用器; 其中，第一多路复用器输入端连接到LC的第一输入端，第二多路复用器输入端连接到LUT输出端，多路复用器输出端连接到LC的第一输出端，​​以及多路复用器 选择端子连接到LC的第二输入端子，以选择出现在第一和第二多路复用器输入端上的哪个信号通过; 其中，通过将一个LC的第一输入端子耦合到另一LC的第一输出端子，形成WLUT链。

    Programmable logic device with two dimensional memory addressing
    5.
    发明授权
    Programmable logic device with two dimensional memory addressing 失效
    具有二维存储器寻址的可编程逻辑器件

    公开(公告)号：US5844854A

    公开(公告)日：1998-12-01

    申请号：US759304

    申请日：1996-12-02

    申请人： Fung Fung Lee

    发明人： Fung Fung Lee

    IPC分类号： G11C8/00 ,  G11C8/12 ,  H03K19/177 ,  G11C13/00

    CPC分类号： H03K19/1776 ,  G11C8/00 ,  G11C8/12

    摘要： A programmable logic array integrated circuit device having a memory array in which data can be accessed in either a transposed or nontransposed mode. The memory array has multiple rows and columns of memory cells. Each row of cells can be viewed as a matrix made up of virtual rows and virtual columns. Data in a given row of the memory array can be accessed using nontransposed data words that contain data bits corresponding to cells in the virtual rows. Data in the given row can also be accessed using transposed data words that contain data bits corresponding to cells in the virtual columns.

    摘要翻译： 一种具有存储器阵列的可编程逻辑阵列集成电路器件，其中数据可以以转置或非转置模式访问。 存储器阵列具有多个存储单元的行和列。 每行单元格可以被视为由虚拟行和虚拟列组成的矩阵。 可以使用包含对应于虚拟行中的单元的数据位的非转置数据字来访问存储器阵列的给定行中的数据。 也可以使用包含与虚拟列中的单元格对应的数据位的转置数据字来访问给定行中的数据。

    Programmable logic array integrated circuits with carry and/or cascade rings
    6.
    发明授权
    Programmable logic array integrated circuits with carry and/or cascade rings 失效
    具有进位和/或级联环的可编程逻辑阵列集成电路

    公开(公告)号：US5672985A

    公开(公告)日：1997-09-30

    申请号：US574351

    申请日：1995-12-18

    申请人： Fung Fung Lee

    发明人： Fung Fung Lee

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704

    摘要： Logic regions in a programmable logic array integrated circuit are interconnected in a closed loop or ring by carry and/or cascade connections. Because such a loop or ring has no ends, a user's logic that uses carry or cascade connections can be placed anywhere along the ring. This eliminates a prior art constraint on the placement of a user's logic on the integrated circuit.

    摘要翻译： 可编程逻辑阵列集成电路中的逻辑区域通过进位和/或级联连接在闭环或环中互连。 因为这样的环或环没有结束，所以使用进位或级联连接的用户逻辑可以放置在环上的任何地方。 这消除了在集成电路上放置用户逻辑的现有技术约束。

    Integrated circuit with improved logic cells
    7.
    发明授权
    Integrated circuit with improved logic cells 有权

    公开(公告)号：US07915917B2

    公开(公告)日：2011-03-29

    申请号：US12753623

    申请日：2010-04-02

    申请人： Fung Fung Lee ,  Wen Zhou

    发明人： Fung Fung Lee ,  Wen Zhou

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17728

    摘要： The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

    Gain matrix for hierarchical circuit partitioning
    9.
    发明授权
    Gain matrix for hierarchical circuit partitioning 失效
    增益矩阵用于分层电路划分

    公开(公告)号：US06212668B1

    公开(公告)日：2001-04-03

    申请号：US08863880

    申请日：1997-05-27

    申请人： John Tse ,  Fung Fung Lee

    发明人： John Tse ,  Fung Fung Lee

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A method for partitioning a group of cells in a network into a set of disjoint blocks of cells. The network is represented by a hierarchical graph with each level representing a hierarchy of resources, leaf nodes representing the blocks of cells, and edges representing interconnections between resources. A gain matrix is formed by combining a gain vector for each level of hierarchy for each possible move. Cells are moved between leaf nodes based on the gain matrix computed.

    摘要翻译： 一种用于将网络中的一组小区划分成一组不相交的小区块的方法。 网络由分层图表示，每个级别表示资源层级，表示单元块的叶节点和表示资源之间互连的边。 通过为每个可能的移动组合用于每层级的增益矢量来形成增益矩阵。 基于计算的增益矩阵，在叶节点之间移动细胞。

    Integrated circuit with improved logic cells
    10.
    发明授权
    Integrated circuit with improved logic cells 有权
    具有改进的逻辑单元的集成电路

    公开(公告)号：US07911228B2

    公开(公告)日：2011-03-22

    申请号：US12753611

    申请日：2010-04-02

    申请人： Fung Fung Lee ,  Wen Zhou

    发明人： Fung Fung Lee ,  Wen Zhou

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17728

    摘要： The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

    摘要翻译： 本发明提供具有改进的逻辑单元的集成电路。 在一个实施例中，提供了具有多个逻辑单元（LC）的集成电路，每个LC包括：具有LUT输出端的查找表; 和第一复用器; 其中，第一多路复用器输入端连接到LC的第一输入端，第二多路复用器输入端连接到LUT输出端，多路复用器输出端连接到LC的第一输出端，​​以及多路复用器 选择端子连接到LC的第二输入端子，以选择出现在第一和第二多路复用器输入端上的哪个信号通过; 其中，通过将一个LC的第一输入端子耦合到另一LC的第一输出端子，形成WLUT链。