公开(公告)号：US09171764B2

公开(公告)日：2015-10-27

申请号：US14106347

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ryan Ryoung Han Kim ,  Jason Cantone

IPC: H01L21/311 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 在一个实施例中，制造集成电路的方法包括蚀刻上心轴层以形成上心轴。 至少一个上心轴具有第一临界尺寸，并且至少一个上心轴具有不等于第一临界尺寸的第二临界尺寸。 该方法还包括在上心轴上形成上间隔件并使用上间隔件作为蚀刻掩模蚀刻下心轴层以形成下心轴。 该方法还包括形成邻近下心轴的下间隔件，并使用下间隔件蚀刻材料作为蚀刻掩模以形成可变间隔的结构。

公开(公告)号：US09431264B2

公开(公告)日：2016-08-30

申请号：US14014906

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Linus Jang ,  Young Joon Moon ,  Ryan Ryoung Han Kim

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823456

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法，其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴，其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

公开(公告)号：US20150170973A1

公开(公告)日：2015-06-18

申请号：US14106347

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ryan Ryoung Han Kim ,  Jason Cantone

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 在一个实施例中，制造集成电路的方法包括蚀刻上心轴层以形成上心轴。 至少一个上心轴具有第一临界尺寸，并且至少一个上心轴具有不等于第一临界尺寸的第二临界尺寸。 该方法还包括在上心轴上形成上间隔件并使用上间隔件作为蚀刻掩模蚀刻下心轴层以形成下心轴。 该方法还包括形成邻近下心轴的下间隔件，并使用下间隔件蚀刻材料作为蚀刻掩模以形成可变间隔的结构。

公开(公告)号：US20150064912A1

公开(公告)日：2015-03-05

申请号：US14014906

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Linus Jang ,  Young Joon Moon ,  Ryan Ryoung Han Kim

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823456

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法，其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴，其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。