公开(公告)号：US10191108B2

公开(公告)日：2019-01-29

申请号：US14945520

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gregory G. Freeman ,  Siyuranga Koswatta ,  Paul S. McLaughlin ,  Daniel J. Poindexter ,  J. Campbell Scott ,  Scott Taylor ,  Gregory Uhlmann ,  James D. Warnock

IPC: G01R33/36 ,  G01R31/28

Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

公开(公告)号：US09285417B2

公开(公告)日：2016-03-15

申请号：US13732482

申请日：2013-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Poindexter ,  James M. Crafts ,  Karre M. Greene ,  Kenneth A. Lavallee ,  Keith C. Stevens

IPC: G01R31/00 ,  G01R31/28 ,  H01L21/00 ,  G01R31/30 ,  H01L23/00

CPC classification number: G01R31/2853 ,  G01R31/30 ,  H01L21/00 ,  H01L24/00 ,  H01M2200/00

Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.

Abstract translation: 使用低电压电流测量的系统和方法来测量集成电路（IC）中的电压网络电流。 一方面，通过一个或多个IC芯片连接器对IC或微芯片施加低电压电流泄漏测试。 基于芯片的电路延迟开发一个或多个规范，其中芯片被中止或者根据芯片的规格是否失败，将其分类为较小的可靠性排序。 或者，低压电流泄漏测试开始集成电路测试流程。 然后施加高电压应力，然后再加入第二次低压漏电试验。 然后，将第二个低电压测试与第一个低V测试进行比较，如果在第二次测试中测量的电流较小，则表明存在可能导致芯片的碎片或降级可靠性的缺陷。

公开(公告)号：US20170146592A1

公开(公告)日：2017-05-25

申请号：US14945520

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gregory G. Freeman ,  Siyuranga Koswatta ,  Paul S. McLaughlin ,  Daniel J. Poindexter ,  J. Campbell Scott ,  Scott Taylor ,  Gregory Uhlmann ,  James D. Warnock

IPC: G01R31/28

CPC classification number: G01R31/2858 ,  G01R31/2884

Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

公开(公告)号：US09552455B2

公开(公告)日：2017-01-24

申请号：US14612683

申请日：2015-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Poindexter ,  Gregory G. Freeman ,  Siyuranga O. Koswatta ,  J. Campbell Scott ,  Leon J. Sigal ,  James D. Warnock

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Abstract translation: 计算库门最大电流限制的有效方法，其中电流限制包括与最大电流相关联的自热效应的影响。 以自我一致的方式获得最大的当前解决方案，提供了一种在没有广泛的数值计算或模拟的情况下以快速方式确定自相矛盾解决方案的方式。 本方法提供了用于表征CMOS设计中使用的大型门库的实用方法。

公开(公告)号：US20160224717A1

公开(公告)日：2016-08-04

申请号：US14612683

申请日：2015-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Poindexter ,  Gregory G. Freeman ,  Siyuranga O. Koswatta ,  J. Campbell Scott ,  Leon J. Sigal ,  James D. Warnock

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Abstract translation: 计算库门最大电流限制的有效方法，其中电流限制包括与最大电流相关联的自热效应的影响。 以自我一致的方式获得最大的当前解决方案，提供了一种在没有广泛的数值计算或模拟的情况下以快速方式确定自相矛盾解决方案的方式。 本方法提供了用于表征CMOS设计中使用的大型门库的实用方法。