公开(公告)号：US10191108B2

公开(公告)日：2019-01-29

申请号：US14945520

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gregory G. Freeman ,  Siyuranga Koswatta ,  Paul S. McLaughlin ,  Daniel J. Poindexter ,  J. Campbell Scott ,  Scott Taylor ,  Gregory Uhlmann ,  James D. Warnock

IPC: G01R33/36 ,  G01R31/28

Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

公开(公告)号：US20170345719A1

公开(公告)日：2017-11-30

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/32 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US20170133923A1

公开(公告)日：2017-05-11

申请号：US14934793

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory G. Freeman ,  Siyuranga O. Koswatta

IPC: H02M1/32

CPC classification number: H03K17/04 ,  H03K19/00315 ,  H03K19/00369

Abstract: An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2nd stage first and second FET devices, each 2nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.

公开(公告)号：US09552455B2

公开(公告)日：2017-01-24

申请号：US14612683

申请日：2015-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Poindexter ,  Gregory G. Freeman ,  Siyuranga O. Koswatta ,  J. Campbell Scott ,  Leon J. Sigal ,  James D. Warnock

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Abstract translation: 计算库门最大电流限制的有效方法，其中电流限制包括与最大电流相关联的自热效应的影响。 以自我一致的方式获得最大的当前解决方案，提供了一种在没有广泛的数值计算或模拟的情况下以快速方式确定自相矛盾解决方案的方式。 本方法提供了用于表征CMOS设计中使用的大型门库的实用方法。

公开(公告)号：US20160224717A1

公开(公告)日：2016-08-04

申请号：US14612683

申请日：2015-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Poindexter ,  Gregory G. Freeman ,  Siyuranga O. Koswatta ,  J. Campbell Scott ,  Leon J. Sigal ,  James D. Warnock

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Abstract translation: 计算库门最大电流限制的有效方法，其中电流限制包括与最大电流相关联的自热效应的影响。 以自我一致的方式获得最大的当前解决方案，提供了一种在没有广泛的数值计算或模拟的情况下以快速方式确定自相矛盾解决方案的方式。 本方法提供了用于表征CMOS设计中使用的大型门库的实用方法。

公开(公告)号：US09953873B2

公开(公告)日：2018-04-24

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/32 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US09906213B2

公开(公告)日：2018-02-27

申请号：US14934793

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory G. Freeman ,  Siyuranga O. Koswatta

IPC: G05F1/00 ,  G05F1/12 ,  G05F1/648 ,  H03K17/04

CPC classification number: H03K17/04 ,  H03K19/00315 ,  H03K19/00369

Abstract: An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2nd stage first and second FET devices, each 2nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.

公开(公告)号：US20170146592A1

公开(公告)日：2017-05-25

申请号：US14945520

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gregory G. Freeman ,  Siyuranga Koswatta ,  Paul S. McLaughlin ,  Daniel J. Poindexter ,  J. Campbell Scott ,  Scott Taylor ,  Gregory Uhlmann ,  James D. Warnock

IPC: G01R31/28

CPC classification number: G01R31/2858 ,  G01R31/2884

Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

公开(公告)号：US09406569B2

公开(公告)日：2016-08-02

申请号：US14519493

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory G. Freeman ,  Kam Leung Lee ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3247 ,  H01L21/76243 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/0623 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Abstract translation: 绝缘体上半导体（SOI）衬底包括体半导体衬底，形成在本体衬底上的掩埋绝缘体层和形成在掩埋绝缘体层上的有源半导体层。 杂质植入到埋入绝缘体层和有源半导体层的界面附近。 在杂质和有源半导体层的上表面之间形成扩散阻挡层。 扩散阻挡层防止杂质从其中扩散。

公开(公告)号：US09305999B2

公开(公告)日：2016-04-05

申请号：US13778419

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/06 ,  H01L29/10 ,  H01L29/84 ,  H01L21/762

CPC classification number: H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract translation: 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。