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公开(公告)号：US10685705B2
公开(公告)日：2020-06-16
申请号：US16047529
申请日：2018-07-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Faraz Khan , Norman W. Robson , Toshiaki Kirihata , Danny Moy , Darren L. Anand
IPC: G11C16/04 , G11C11/56 , H01L29/792 , H01L27/11573 , H01L29/73 , G11C16/10 , G11C16/14
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.
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公开(公告)号：US10535379B2
公开(公告)日：2020-01-14
申请号：US15695457
申请日：2017-09-05
Applicant: GLOBALFOUNDRIES INC.
Inventor： Darren L. Anand , John A. Fifield , Eric D. Hunt-Schroeder , Mark D. Jacunski
Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
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公开(公告)号：US10395752B2
公开(公告)日：2019-08-27
申请号：US15730078
申请日：2017-10-11
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric D. Hunt-Schroeder , Darren L. Anand
IPC: G11C16/04 , G11C29/50 , H01L27/11517
Abstract: The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.
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Patent Agency Ranking
4.发明授权Voltage-aware adaptive static random access memory (SRAM) write assist circuit 有权电压感知自适应静态随机存取存储器（SRAM）写辅助电路公开(公告)号：US09508420B1
公开(公告)日：2016-11-29
申请号：US15009132
申请日：2016-01-28
Applicant: GLOBALFOUNDRIES INC.
Inventor： Eric D. Hunt-Schroeder , John A. Fifield , Darren L. Anand , Kevin A. Batson
IPC: G11C5/14 , G11C11/419
CPC classification number: G11C11/419
Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.
Abstract translation: 提供写辅助电路的方法。 写辅助电路包括多个二进制加权升压电容器，每个二进制加权升压电容器包含耦合到位线的第一节点和连接到相应升压使能晶体管的第二节点，以及多个升压使能晶体管，每个包含连接到升压器的栅极 用于控制相应的二进制加权升压电容器的控制使能信号。 多个升压启动晶体管中的每一个的升压控制使能信号由基于电源电平的编码值来控制。
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5.发明授权公开(公告)号：US10468104B1
公开(公告)日：2019-11-05
申请号：US16007445
申请日：2018-06-13
Applicant: GLOBALFOUNDRIES INC.
Inventor： Darren L. Anand , William Roy John Corbin
Abstract: The present disclosure relates to a structure which includes a pair of non-volatile storage devices in a memory array which are sensed to determine an initial data state and reinforced by a write operation of the initial data state to the pair of non-volatile storage devices. The structure can be used for a robust and error free physical unclonable function.
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公开(公告)号：US10163526B2
公开(公告)日：2018-12-25
申请号：US15920677
申请日：2018-03-14
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric D. Hunt-Schroeder , Darren L. Anand
Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.
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公开(公告)号：US10062445B2
公开(公告)日：2018-08-28
申请号：US15367815
申请日：2016-12-02
Applicant: GLOBALFOUNDRIES INC.
Inventor： Eric D. Hunt-Schroeder , Steven Lamphier , Darren L. Anand
CPC classification number: G11C17/18 , G11C8/14 , G11C17/16 , G11C29/26 , G11C2029/2602
Abstract: The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.
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公开(公告)号：US09953727B1
公开(公告)日：2018-04-24
申请号：US15430170
申请日：2017-02-10
Applicant: GLOBALFOUNDRIES INC.
Inventor： John A. Fifield , Eric D. Hunt-Schroeder , Darren L. Anand
CPC classification number: G11C29/78 , G11C17/16 , G11C17/18 , G11C29/50 , G11C29/50008 , G11C29/822 , G11C2029/5002 , G11C2029/5006
Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.
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