公开(公告)号：US20180047727A1

公开(公告)日：2018-02-15

申请号：US15234762

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charan V. SURISETTY ,  Dominic J. SCHEPIS ,  Kangguo CHENG ,  Alexander REZNICEK

IPC: H01L27/088 ,  H01L21/3105 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791

Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.

公开(公告)号：US20200185510A1

公开(公告)日：2020-06-11

申请号：US16789936

申请日：2020-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic J. SCHEPIS ,  Alexander REZNICEK

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/78

Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices. A doped silicon substrate, a first insulator over the doped silicon substrate, a gate conductor over the first insulator, and a second insulator over the gate conductor. Silicon nanowires extend from the top surface of the substrate through the first insulator, the gate conductor, and the second insulator. A first contact extends from the gate conductor through the second insulator, a second contact extends from the substrate through the first insulator, the gate conductor, and the second insulator layer, and an insulating spacer material is positioned between the second contact and the gate conductor.

公开(公告)号：US20180233583A1

公开(公告)日：2018-08-16

申请号：US15433141

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic J. SCHEPIS ,  Alexander REZNICEK

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/7827 ,  H01L29/78642

Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.

公开(公告)号：US20160163826A1

公开(公告)日：2016-06-09

申请号：US14564323

申请日：2014-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Alexander REZNICEK ,  Dominic J. SCHEPIS

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.

Abstract translation: 一种方法，包括在由半导体衬底制成的半导体鳍片的相对侧壁上形成翅片间隔件，形成与翅片间隔件直接接触的电介质层，使得翅片的顶表面和翅片间隔件的顶表面保持暴露，凹陷 翅片间隔件的一部分，去除翅片间隔件以形成开口，并且在开口中外延生长未熔化的源极漏极区域，其中未熔化的源极漏极区域的横向生长通过电介质层约束在相对的两侧。