公开(公告)号：US10651284B2

公开(公告)日：2020-05-12

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US10586762B2

公开(公告)日：2020-03-10

申请号：US15860171

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Lars W. Liebmann

IPC: H01L23/522 ,  H01L21/28 ,  H01L23/538

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.

公开(公告)号：US20190378900A1

公开(公告)日：2019-12-12

申请号：US16548335

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45

Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

公开(公告)号：US20190148240A1

公开(公告)日：2019-05-16

申请号：US16243863

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

公开(公告)号：US20190123162A1

公开(公告)日：2019-04-25

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US20190035692A1

公开(公告)日：2019-01-31

申请号：US15658524

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Bipul C. Paul ,  Daniel Chanemougame ,  Nigel G. Cave

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first gate structure above a first region of a semiconducting substrate. A first sidewall spacer is formed adjacent the first gate structure. The first gate structure and the first sidewall spacer are recessed to define a first gate contact cavity. A second sidewall spacer is formed in the first gate contact cavity. A first conductive gate contact is formed in the first gate contact cavity. The second sidewall spacer is removed to define a first spacer cavity. A conductive material is formed in the first spacer cavity to form a first conductive spacer contacting the first conductive gate contact.

公开(公告)号：US20180286956A1

公开(公告)日：2018-10-04

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L29/41775 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66545

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US09941163B2

公开(公告)日：2018-04-10

申请号：US15618880

申请日：2017-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170104100A1

公开(公告)日：2017-04-13

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V.V.S. Surisetty ,  Mickey H. Yu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

公开(公告)号：US20170047418A1

公开(公告)日：2017-02-16

申请号：US14822490

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Su Chen Fan ,  Lars W. Liebmann ,  Ruilong Xie

IPC: H01L29/45 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/7827 ,  H01L2221/1063

Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.

Abstract translation: 形成栅极结合的方法包括暴露有源区以形成沟槽接触开口并在其中形成沟槽接触。 在沟槽触点和相邻栅极结构的间隔物上形成蚀刻停止层。 沉积层间电介质（ILD）以填满蚀刻停止层。 栅极结构的一侧上的ILD和蚀刻停止层被打开以提供暴露的蚀刻停止层部分。 栅极结构凹陷以露出栅极导体。 去除暴露的蚀刻停止层部分。 沉积导电材料以提供与栅极结构一侧上的沟槽接触的自对准接触，以形成到栅极导体下方的栅极接触，并且在ILD之间的有效区域之间形成水平连接 栅极导体和自对准触点。