公开(公告)号：US20200335602A1

公开(公告)日：2020-10-22

申请号：US16390473

申请日：2019-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tao Chu ,  Rongtao Lu ,  Ayse M. Ozbek ,  Wei Ma ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

公开(公告)号：US10755982B1

公开(公告)日：2020-08-25

申请号：US16508816

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abu Naser M. Zainuddin ,  Wei Ma ,  Daniel Jaeger ,  Joseph Versaggi ,  Jae Gon Lee ,  Thomas Kauerauf

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.

公开(公告)号：US20200321332A1

公开(公告)日：2020-10-08

申请号：US16376234

申请日：2019-04-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abu Naser M. Zainuddin ,  Christopher D. Sheraw ,  Sangameshwar Rao Saudari ,  Wei Ma ,  Kai Zhao ,  Bala S. Haran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.

公开(公告)号：US20200273953A1

公开(公告)日：2020-08-27

申请号：US16287365

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Chu ,  Wei Ma ,  Jae Gon Lee ,  Hong Yu ,  Zhenyu Hu ,  Srikanth Balaji Samavedam

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: One illustrative integrated circuit product disclosed herein includes a short-channel transistor device and a long-channel transistor device formed above a semiconductor substrate, wherein a first gate structure for the short-channel transistor device includes a short-channel WFM layer with a first upper surface that is positioned at a first distance above an upper surface of the semiconductor substrate, and wherein a second gate structure for the long-channel transistor device includes a long-channel WFM layer with a second upper surface that is positioned at a second distance above the upper surface of the semiconductor substrate, wherein the first distance is greater than the second distance.

公开(公告)号：US10833169B1

公开(公告)日：2020-11-10

申请号：US16390473

申请日：2019-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tao Chu ,  Rongtao Lu ,  Ayse M. Ozbek ,  Wei Ma ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/321

Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.