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    Metal gate for a field effect transistor and method
    1.
    发明授权
    Metal gate for a field effect transistor and method 有权

    公开(公告)号：US10833169B1

    公开(公告)日：2020-11-10

    申请号：US16390473

    申请日：2019-04-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tao Chu ,  Rongtao Lu ,  Ayse M. Ozbek ,  Wei Ma ,  Haiting Wang

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/321

    Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

    METAL GATE FOR A FIELD EFFECT TRANSISTOR AND METHOD
    3.
    发明申请
    METAL GATE FOR A FIELD EFFECT TRANSISTOR AND METHOD 审中-公开

    公开(公告)号：US20200335602A1

    公开(公告)日：2020-10-22

    申请号：US16390473

    申请日：2019-04-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tao Chu ,  Rongtao Lu ,  Ayse M. Ozbek ,  Wei Ma ,  Haiting Wang

    IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

    Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

    METHODS OF FORMING SOURCE/DRAIN REGIONS OF A FINFET DEVICE AND THE RESULTING STRUCTURES
    5.
    发明申请
    METHODS OF FORMING SOURCE/DRAIN REGIONS OF A FINFET DEVICE AND THE RESULTING STRUCTURES 有权

    公开(公告)号：US20210020515A1

    公开(公告)日：2021-01-21

    申请号：US16515638

    申请日：2019-07-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Bingwu Liu ,  Tao Chu ,  Man Gu

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

    Abstract: One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

    METHODS OF FORMING AN IC PRODUCT COMPRISING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGE LEVELS
    6.
    发明申请
    METHODS OF FORMING AN IC PRODUCT COMPRISING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGE LEVELS 审中-公开

    公开(公告)号：US20200286790A1

    公开(公告)日：2020-09-10

    申请号：US16296469

    申请日：2019-03-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Wei Hong ,  Hong Yu ,  Tao Chu ,  Bingwu Liu

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

    Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

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