公开(公告)号：US20190131452A1

公开(公告)日：2019-05-02

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Hong YU ,  Xinyuan DOU ,  Xusheng WU ,  Dongil CHOI ,  Edmund K. BANGHART ,  Md Khaled HASSAN

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US20200135545A1

公开(公告)日：2020-04-30

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. SRIVASTAVA ,  Sipeng GU ,  Sunil K. SINGH ,  Xinyuan DOU ,  Akshey SEHGAL ,  Zhiguo SUN

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US20180330995A1

公开(公告)日：2018-11-15

申请号：US16026840

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan DOU ,  Hong YU ,  Zhenyu HU ,  Xing ZHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/42376

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.