公开(公告)号：US20180330995A1

公开(公告)日：2018-11-15

申请号：US16026840

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan DOU ,  Hong YU ,  Zhenyu HU ,  Xing ZHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/42376

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US20160049495A1

公开(公告)日：2016-02-18

申请号：US14461887

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kristina TREVINO ,  Yuan-Hung LIU ,  Gabriel Padron WELLS ,  Xing ZHANG ,  Hoong Shing WONG ,  Chang Ho MAENG ,  Taejoon HAN ,  Gowri KAMARTHY ,  Isabelle ORAIN ,  Ganesh UPADHYAYA

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract translation: 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。