公开(公告)号：US20200135545A1

公开(公告)日：2020-04-30

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. SRIVASTAVA ,  Sipeng GU ,  Sunil K. SINGH ,  Xinyuan DOU ,  Akshey SEHGAL ,  Zhiguo SUN

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US20160365277A1

公开(公告)日：2016-12-15

申请号：US14740035

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qiang FANG ,  Zhiguo SUN ,  Jiehui SHU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53238

Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.

Abstract translation: 用于电耦合一个或多个下层半导体器件的起始金属化结构，所述结构包括介电材料的底层，其中位于其中的金属填充通孔，底层上的保护层和介电材料的顶层 保护层。 在电介质材料的顶层上形成非晶硅的牺牲层，在牺牲层上方形成保护层，并且通过穿过金属填充的通孔上方的每个层的通孔，以暴露金属 - 通过（s）填充。 然后选择性地去除保护层，以及非晶硅的牺牲层。

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US20160005598A1

公开(公告)日：2016-01-07

申请号：US14321866

申请日：2014-07-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng GU ,  Sandeep GAAN ,  Zhiguo SUN ,  Huang LIU ,  Adam SELSLEY

IPC: H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/321

Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Abstract translation: 提供了一种用于制造分层电路结构的方法，其包括例如：在衬底上沉积第一材料层，第一材料层具有氧化的上表面; 在所述第一材料层的氧化的上表面上提供第二材料层; 并且在第二材料层在第一材料层的氧化的上表面上提供第二材料层期间，抑制一个或多个元件从第一材料层的氧化的上表面扩散到第一材料层或第二材料层中。 抑制可以包括一个或多个修饰第一材料层的特征，在第一材料层的氧化的上表面上形成保护层，或改变在提供第二材料层中使用的至少一个工艺参数。

公开(公告)号：US20190206729A1

公开(公告)日：2019-07-04

申请号：US15860318

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang FANG ,  Shafaat AHMED ,  Zhiguo SUN ,  Jiehui SHU ,  Dinesh R. KOLI ,  Wei-Tsu TSENG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

公开(公告)号：US20180166383A1

公开(公告)日：2018-06-14

申请号：US15377592

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy CAO ,  Zhiguo SUN ,  Joseph F. SHEPARD, JR. ,  Moosung M. CHAE

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

公开(公告)号：US20150357292A1

公开(公告)日：2015-12-10

申请号：US14799624

申请日：2015-07-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei LIU ,  Zhiguo SUN ,  Huang LIU ,  Jin Ping LIU

IPC: H01L23/00 ,  H01L21/3115

CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

公开(公告)号：US20150263169A1

公开(公告)日：2015-09-17

申请号：US14207822

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng GU ,  Zhiguo SUN ,  Sandeep GAAN ,  Danni CHEN ,  Wen-Pin PENG ,  Huang LIU

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Abstract translation: 提供半导体结构和制造方法，其具有桥接膜，其有助于介电材料的下层和上覆的应力诱导层的粘附。 该方法包括例如在半导体衬底上提供其中设置有至少一个栅极结构的电介质材料层; 在所述介​​电材料层上提供具有所述至少一个栅极结构的桥接膜; 并在桥接膜上提供应力诱导层。 选择桥接膜以便于通过部分地与电介质材料层形成化学键而使介电材料的下层和上覆的应力诱导层两者粘附，而不与应力诱导层形成化学键 。

公开(公告)号：US20150171001A1

公开(公告)日：2015-06-18

申请号：US14106340

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Daniel SMITH ,  Kumarapuram GOPALAKRISHNAN ,  Hung-Wei LIU

IPC: H01L23/498 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033

CPC classification number: H01L21/32051 ,  H01L21/3081 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with a protection layer for a dielectric mask layer are provided. One method includes, for instance; obtaining a substrate having at least one of a dielectric layer and a metal layer; forming a first SiCN dielectric mask layer on a top surface of at least one of the dielectric layer and a metal layer; and forming a silicon nitride (SiNx) cap layer on a top surface of the first SiCN dielectric mask layer. One intermediate semiconductor device includes, for instance: a substrate having at least one of a dielectric layer and a metal layer; a first SiCN dielectric mask layer on a top surface of at least one of the dielectric layer and a metal layer; and a silicon nitride (SiNx) cap layer on a top surface of the first SiCN dielectric mask layer.

Abstract translation: 提供了用于形成具有用于介电掩模层的保护层的半导体器件的器件和方法。 一种方法包括： 获得具有电介质层和金属层中的至少一个的衬底; 在所述电介质层和金属层中的至少一个的顶表面上形成第一SiCN电介质掩模层; 以及在所述第一SiCN介电掩模层的顶表面上形成氮化硅（SiNx）覆盖层。 一个中间半导体器件包括例如：具有电介质层和金属层中的至少一个的衬底; 在所述电介质层和金属层中的至少一个的顶表面上的第一SiCN介电掩模层; 和在第一SiCN介电掩模层的顶表面上的氮化硅（SiNx）覆盖层。

公开(公告)号：US20150123250A1

公开(公告)日：2015-05-07

申请号：US14070823

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei LIU ,  Zhiguo SUN ,  Huang LIU ,  Jin Ping LIU

IPC: H01L21/311 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

Abstract translation: 提供了有助于制造无缺陷半导体结构的方法，其包括例如：提供介电层，该电介质层包括至少一种可消耗材料; 选择性地去除所述电介质层的一部分，其中所述选择性去除部分地消耗所述至少一种可消耗材料的剩余部分，在所述电介质层的剩余部分内留下耗尽区; 并且对所述介质层的所述耗尽区进行处理处理，以用至少一种替代的可消耗材料恢复所述耗尽区，从而有助于制造无缺陷的半导体结构。