公开(公告)号：US10396078B2

公开(公告)日：2019-08-27

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US09634084B1

公开(公告)日：2017-04-25

申请号：US15040477

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christopher D. Sheraw ,  Chengwen Pei ,  Eric T. Harley ,  Yue Ke ,  Henry K. Utomo ,  Yinxiao Yang ,  Zhibin Ren

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0615 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

公开(公告)号：US09536985B2

公开(公告)日：2017-01-03

申请号：US14499356

申请日：2014-09-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract translation: 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。

公开(公告)号：US20180286863A1

公开(公告)日：2018-10-04

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US10020307B1

公开(公告)日：2018-07-10

申请号：US15429502

申请日：2017-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L21/8249 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211

Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.