公开(公告)号：US09595518B1

公开(公告)日：2017-03-14

申请号：US14969449

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I-Chih Chou ,  Chengwen Pei ,  Edward P. Maciejewski ,  Ning Zhan

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/265 ,  H01L49/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823431 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/7851

Abstract: Fabrication methods and structure include: providing a wafer with at least one fin extended above a substrate in a first region, and at least one fin extended above the substrate in a second region of the wafer; forming a gate structure extending at least partially over the at least one fin to define a semiconductor device region in the first region; implanting a dopant into the at least one fin in the first region and into the at least one fin in the second region of the wafer, where the implanting of the dopant into the at least one fin of the second region modulates a physical property of the at least one fin to define a resistor device region in the second region; and disposing a conductive material at least partially over the at least one fin in the first region and over the at least one fin in the second region of the wafer, in part, to form a source and drain contact in the first region, and a fin-type metal-semiconductor resistor in the second region.

Abstract translation: 制造方法和结构包括：提供具有在第一区域中的衬底上延伸的至少一个翅片的晶片和在晶片的第二区域中在衬底上方延伸的至少一个鳍; 形成至少部分地在所述至少一个翅片上延伸的栅极结构，以在所述第一区域中限定半导体器件区域; 将掺杂剂注入所述第一区域中的所述至少一个翅片并且进入所述晶片的所述第二区域中的所述至少一个翅片，其中所述掺杂剂注入到所述第二区域的所述至少一个翅片中调制所述第二区域的物理性质 至少一个翅片以限定所述第二区域中的电阻器件区域; 以及至少部分地在所述第一区域中的所述至少一个翅片上并且在所述晶片的所述第二区域中的所述至少一个翅片之上至少部分地布置导电材料，以部分地在所述第一区域中形成源极和漏极接触，以及 鳍式金属半导体电阻器。

公开(公告)号：US09269786B2

公开(公告)日：2016-02-23

申请号：US14037423

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I-Chih Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Claude Ortolland ,  Kai Zhao

IPC: H01L29/76 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.

Abstract translation: 使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极 电介质和半导体沟道区。 栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。 通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。