公开(公告)号：US20160328511A1

公开(公告)日：2016-11-10

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: G06F17/50 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Abstract translation: 公开了在IC设计的布局中所选择的区域（例如，包括关键区域）的识别和部分重新路由的方法以及所得到的设备。 实施例包括将IC器件的设计数据与制造IC器件的制造工艺标准进行比较; 在设计数据中，至少部分地基于所述布局区域中的金属段，互连段或其组合的接近来识别布局区域; 在所述布局区域中执行部分重路由以基本上满足所述准则，其中至少一个互连元件被移位或扩展; 并将部分重新路由集成到用于制造过程中的设计数据中。

公开(公告)号：US20160124308A1

公开(公告)日：2016-05-05

申请号：US14533464

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guoxiang NING ,  Xintuo DAI ,  Huang LIU ,  Chin Teong LIM

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/0035 ,  G03F7/094 ,  G03F7/2024 ,  G03F7/203

Abstract: Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.

Abstract translation: 促进电路结构的制造，其中使用第一掩模进行多层结构的第一曝光，第一掩模限定要形成在多层结构的基板上方的元件的至少一个边缘的定位。 使用限定元件的至少一个其它边缘的定位的第二掩模来执行多层结构的第二曝光。 至少部分地使用所述元件的至少一个边缘和所述至少一个其它边缘的限定的定位来移除所述多层结构的至少一些材料，以在所述基底上方形成所述元件。 在一些示例中，形成多个元件，多个元件是硬掩模元件，以便蚀刻工艺来蚀刻衬底材料。

公开(公告)号：US20160161840A1

公开(公告)日：2016-06-09

申请号：US14560388

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chin Teong LIM ,  Guoxiang NING ,  Paul ACKMANN

IPC: G03F1/36

CPC classification number: G03F1/36

Abstract: Methods of calibrating an OPC model using converged results of CD measurements from at least two locations along a substrate profile of a 1D, 2D, or critical area structure are provided. Embodiments include calibrating an OPC model for a structure to be formed in a substrate; simulating a CD of the structure at at least two locations along a substrate profile of the structure using the OPC model; comparing the simulated CD of the structure at each location against a corresponding measured CD; recalibrating the OPC model based on the comparing of each simulated CD against the corresponding measured CD; repeating the steps of simulating, comparing, and recalibrating until comparing at a first of the at least two locations converges to a first criteria and comparing at each other of the at least two locations converges to a corresponding criteria; and forming the structure using the recalibrated OPC model.

Abstract translation: 提供了使用来自沿着1D，2D或临界区域结构的衬底轮廓的至少两个位置的CD测量的收敛结果来校准OPC模型的方法。 实施例包括校准用于要在基板中形成的结构的OPC模型; 使用OPC模型在结构的衬底轮廓的至少两个位置处模拟结构的CD; 将每个位置的结构的模拟CD与相应的测量CD进行比较; 基于每个模拟CD与对应的测量CD的比较重新校准OPC模型; 重复模拟，比较和重新校准的步骤，直到在至少两个位置的第一个位置比较收敛到第一标准，并且至少两个位置处的彼此的比较收敛到相应的标准; 并使用重新校准的OPC模型形成结构。

公开(公告)号：US20150310157A1

公开(公告)日：2015-10-29

申请号：US14263340

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Guoxiang NING ,  Paul ACKMANN ,  Chin Teong LIM

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Abstract translation: 公开了用于使OPC模型能够解决掩模中的错误的方法和装置。 实施例包括：确定电路设计的图形层; 估计在制造的电路中指示用于形成图案化层的制造掩模的掩模角舍入误差的穿透比; 以及基于所述穿透比，由处理器确定所述电路设计的光学邻近校正的补偿度量。

公开(公告)号：US20150192866A1

公开(公告)日：2015-07-09

申请号：US14146771

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Christopher SPENCE ,  Paul ACKMANN ,  Chin Teong LIM

IPC: G03F7/20

CPC classification number: G03F7/70441 ,  G03F1/70 ,  Y02T10/82

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract translation: 公开了一种用于高效光学邻近校正（OPC）修复流程的方法和装置。 实施例可以包括接收集成电路（IC）设计布局的输入数据流，对输入数据流执行OPC步骤的一个或多个迭代和布局抛光步骤，以及如果最后一个输出的输出执行智能增强步骤 OPC步骤的迭代不能满足一个或多个布局标准，并且如果一个或多个迭代的数量满足阈值。 附加实施例可以包括执行与OPC步骤交联的模式插入过程，模式插入过程是基本光学规则检查（ORC）过程。

公开(公告)号：US20170186687A1

公开(公告)日：2017-06-29

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  G03F1/36

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20170061044A1

公开(公告)日：2017-03-02

申请号：US14841037

申请日：2015-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guo Xiang NING ,  Yuping REN ,  David POWER ,  Lalit SHOKEEN ,  Chin Teong LIM ,  Paul W. ACKMANN ,  Xiang HU

IPC: G06F17/50 ,  G03F1/36 ,  G05B15/02

CPC classification number: G06F17/5009 ,  G03F1/36 ,  G06F17/5081

Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

Abstract translation: 提供了用于产生用于OPC或MPC工艺流程的最终电介质蚀刻补偿表和最终硬掩模蚀刻补偿表的方法和装置。 实施例包括在晶片上执行重叠图案分类; 基于图案分类来校准电介质蚀刻偏压或硬掩模蚀刻偏压; 将通孔层与金属层的CD重叠与通孔层的CD重叠与金属层的下连接金属层或CD重叠与上连接通孔层和金属层的CD重叠与 通过层反对标准; 将最终介电蚀刻补偿和硬掩模蚀刻补偿表输出到OPC或MPC工艺流程; 并重复校准，比较和输出剩余的通孔层或金属层的步骤。

公开(公告)号：US20160125121A1

公开(公告)日：2016-05-05

申请号：US14533497

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Xintuo DAI ,  Huang LIU ,  Chin Teong LIM

IPC: G06F17/50 ,  G03F7/34 ,  G03F7/32 ,  G03F7/16 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/34

Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

Abstract translation: 实现基于抗蚀剂特性的特征的关键尺寸目标。 建立掩模数据用于制造光刻掩模以将抗蚀剂的不同区域暴露于高，低和中等曝光水平。 抗蚀剂被配置为当暴露于高或低曝光水平时表现出高溶解度，并且当暴露于中等曝光水平时具有低溶解度。 确定抗蚀剂暴露于中间曝光水平的区域的关键尺寸，并且建立掩模数据以指示用于在光刻掩模上形成的不透明区域。 排列不透明区域以便于将抗蚀剂的区域暴露于中间曝光水平，以获得确定的临界尺寸。 此外，提供了一种用于从衬底材料上方的掩模层原位形成图案化掩模的方法。