公开(公告)号：US20180204840A1

公开(公告)日：2018-07-19

申请号：US15407960

申请日：2017-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei PENG ,  Xusheng WU

IPC: H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/6681

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.

公开(公告)号：US20180190817A1

公开(公告)日：2018-07-05

申请号：US15393400

申请日：2016-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  David Paul BRUNCO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/66795

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20160163859A1

公开(公告)日：2016-06-09

申请号：US14560428

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Hongxiang MO ,  Qi ZHANG ,  Byoung-Gi MIN ,  Jeasung PARK

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/30604 ,  H01L21/823462 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack.

Abstract translation: 公开了在伪栅极去除期间使用氮化物来保护源极/漏极区域的方法以及所得到的器件。 实施例包括在基板上形成氧化物层; 在氧化物层上形成氮化物保护层; 在氮化物保护层上形成虚拟栅极层; 图案化在衬底的第一和第二部分上形成第一和第二虚拟栅极堆叠的氧化物，氮化物和伪栅极层，每个伪栅极堆叠包括伪栅极，氮化物保护层和氧化物层，其中一部分 氧化物层沿着衬底延伸超过虚拟栅极的侧边缘; 在第一和第二伪栅极堆叠的相对侧分别在衬底中形成第一和第二源极/漏极空腔; 分别在第一和第二源极/漏极腔中生长第一和第二eSiGe源极/漏极区域; 以及去除第一伪栅极和第二虚拟栅极堆叠。

公开(公告)号：US20160126316A1

公开(公告)日：2016-05-05

申请号：US14526831

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jin Ping LIU ,  Min-hwa CHI

IPC: H01L29/165 ,  H01L29/737 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

Abstract translation: 提供晶体管结构和制造晶体管结构的方法。 所述方法包括：至少部分地在衬底内制造晶体管结构，所述制造包括：在所述衬底内提供空腔; 以及至少部分地在所述空腔内形成所述晶体管结构的第一部分和第二部分，所述第一部分至少部分地设置在所述基板和所述第二部分之间，其中所述第一部分禁止材料从所述第二部分扩散到所述第二部分 基质。 在一个实施例中，晶体管结构是场效应晶体管结构，并且第一部分和第二部分包括场效应晶体管结构的源极区或漏极区之一。 在另一实施例中，晶体管结构是双极结型晶体管结构。

公开(公告)号：US20190385914A1

公开(公告)日：2019-12-19

申请号：US16007023

申请日：2018-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  David Paul BRUNCO

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L27/088

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20170186687A1

公开(公告)日：2017-06-29

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  G03F1/36

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20170084718A1

公开(公告)日：2017-03-23

申请号：US15367366

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Min-hwa CHI ,  Edmund Kenneth BANGHART

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

公开(公告)号：US20200258789A9

公开(公告)日：2020-08-13

申请号：US16007023

申请日：2018-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  David Paul BRUNCO

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L27/088

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20180158821A1

公开(公告)日：2018-06-07

申请号：US15370555

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Changyong XIAO ,  Xusheng WU ,  Min-hwa CHI ,  Jie CHEN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures with low resistance and methods of manufacture. The structure includes: an nFET device formed in a first cavity having a first volume which is filled with conductive material; and a pFET device forming in a second cavity having a second volume greater than the first volume. The second volume being filled with the conductive material.