公开(公告)号：US20150325445A1

公开(公告)日：2015-11-12

申请号：US14270995

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui SHU ,  Huang LIU

IPC: H01L21/28 ,  H01L21/311 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L21/28035 ,  H01L21/28238 ,  H01L21/31116 ,  H01L29/401

Abstract: An improved method for fabricating a semiconductor device is provided to decrease substrate gouging during oxide spacer formation. The method includes: forming a gate structure on a substrate; depositing an oxide layer along the sidewalls of the gate structure and on the substrate; removing some of the oxide layer to define oxide spacers along sidewalls of the gate structure; and performing an isotropic etch process to remove a residual portion of the oxide layer.

Abstract translation: 提供了一种用于制造半导体器件的改进方法，用于在氧化物间隔物形成期间减少衬底气刨。 该方法包括：在基板上形成栅极结构; 沿着栅极结构的侧壁和衬底上沉积氧化物层; 去除所述氧化物层中的一些以在所述栅极结构的侧壁上限定氧化物间隔物; 并执行各向同性蚀刻工艺以除去氧化物层的残留部分。

公开(公告)号：US20150270159A1

公开(公告)日：2015-09-24

申请号：US14220260

申请日：2014-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Hongliang SHEN ,  Huang LIU ,  Tao HAN ,  Xiang HU

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/76229 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111

Abstract: Semiconductor structure fabrication methods are provided which include: forming one or more trenches and a plurality of plateaus within a substrate structure; providing a conformal stop layer over the substrate structure, including over the plurality of plateaus, the conformal stop layer being or including oxidized polycrystalline silicon; depositing a material over the substrate structure to fill the one or more trenches and cover the plurality of plateaus thereof; and planarizing the material using a slurry to form coplanar surfaces of the material and the conformal stop layer, wherein the slurry reacts with the oxidized polycrystalline silicon of the conformal stop layer to facilitate providing the coplanar surfaces with minimal dishing of the material. Various embodiments are provided, including different methods of providing the conformal stop layer, such as by oxidizing at least an upper portion of polycrystalline silicon, or by performing an in-situ steam growth process.

Abstract translation: 提供半导体结构制造方法，其包括：在衬底结构内形成一个或多个沟槽和多个平台; 在所述衬底结构上提供保形停止层，包括在所述多个平台上，所述共形停止层包括氧化的多晶硅; 在衬底结构上沉积材料以填充所述一个或多个沟槽并覆盖其多个平台; 并且使用浆料平坦化材料以形成材料和共形停止层的共面表面，其中浆料与保形停止层的氧化多晶硅反应，以便于提供最小的凹陷的共面表面。 提供了各种实施例，包括提供保形停止层的不同方法，例如通过氧化至少多晶硅的上部，或者通过进行原位蒸汽生长过程。

公开(公告)号：US20150357292A1

公开(公告)日：2015-12-10

申请号：US14799624

申请日：2015-07-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei LIU ,  Zhiguo SUN ,  Huang LIU ,  Jin Ping LIU

IPC: H01L23/00 ,  H01L21/3115

CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

公开(公告)号：US20150263169A1

公开(公告)日：2015-09-17

申请号：US14207822

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng GU ,  Zhiguo SUN ,  Sandeep GAAN ,  Danni CHEN ,  Wen-Pin PENG ,  Huang LIU

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Abstract translation: 提供半导体结构和制造方法，其具有桥接膜，其有助于介电材料的下层和上覆的应力诱导层的粘附。 该方法包括例如在半导体衬底上提供其中设置有至少一个栅极结构的电介质材料层; 在所述介​​电材料层上提供具有所述至少一个栅极结构的桥接膜; 并在桥接膜上提供应力诱导层。 选择桥接膜以便于通过部分地与电介质材料层形成化学键而使介电材料的下层和上覆的应力诱导层两者粘附，而不与应力诱导层形成化学键 。

公开(公告)号：US20150123250A1

公开(公告)日：2015-05-07

申请号：US14070823

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei LIU ,  Zhiguo SUN ,  Huang LIU ,  Jin Ping LIU

IPC: H01L21/311 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

Abstract translation: 提供了有助于制造无缺陷半导体结构的方法，其包括例如：提供介电层，该电介质层包括至少一种可消耗材料; 选择性地去除所述电介质层的一部分，其中所述选择性去除部分地消耗所述至少一种可消耗材料的剩余部分，在所述电介质层的剩余部分内留下耗尽区; 并且对所述介质层的所述耗尽区进行处理处理，以用至少一种替代的可消耗材料恢复所述耗尽区，从而有助于制造无缺陷的半导体结构。

公开(公告)号：US20200020769A1

公开(公告)日：2020-01-16

申请号：US16032878

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei PENG ,  Sang Woo LIM ,  Matthew Wahlquist STOKER ,  Huang LIU ,  Jinping LIU

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3x fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3x fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

公开(公告)号：US20160005598A1

公开(公告)日：2016-01-07

申请号：US14321866

申请日：2014-07-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng GU ,  Sandeep GAAN ,  Zhiguo SUN ,  Huang LIU ,  Adam SELSLEY

IPC: H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/321

Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Abstract translation: 提供了一种用于制造分层电路结构的方法，其包括例如：在衬底上沉积第一材料层，第一材料层具有氧化的上表面; 在所述第一材料层的氧化的上表面上提供第二材料层; 并且在第二材料层在第一材料层的氧化的上表面上提供第二材料层期间，抑制一个或多个元件从第一材料层的氧化的上表面扩散到第一材料层或第二材料层中。 抑制可以包括一个或多个修饰第一材料层的特征，在第一材料层的氧化的上表面上形成保护层，或改变在提供第二材料层中使用的至少一个工艺参数。

公开(公告)号：US20150380246A1

公开(公告)日：2015-12-31

申请号：US14315659

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang HU ,  Yuping REN ,  Duohui BEI ,  Sipeng GU ,  Huang LIU

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/538

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract translation: 提供了用于在电路结构上的尺寸控制的通孔形成的方法，包括在多个相邻的导电结构上。 所述方法包括例如在电路结构之上提供图案化的多层堆叠结构，所述堆叠结构包括至少一层，以及在所述至少一层上方的图案转移层，所述图案转移层被图案化 至少有一个通孔; 在所述至少一个通孔开口内提供侧壁间隔层，以形成至少一个尺寸控制的通孔开口; 以及使用所述至少一个尺寸控制的通孔开口蚀刻穿过所述堆叠结构的所述至少一个层，以便于在所述电路结构上提供通孔。 在一个实施方案中，堆叠结构包括设置在电介质层和平坦化层之间的图案化硬掩模层内的沟槽开口，并且通孔部分地自对准沟槽。

公开(公告)号：US20150194342A1

公开(公告)日：2015-07-09

申请号：US14150260

申请日：2014-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy CAO ,  Songkram SRIVATHANAKUL ,  Huang LIU ,  Garo Jacques DERDERIAN ,  Boaz ALPERSON

IPC: H01L21/768 ,  H01L23/482

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract translation: 提供电路结构的导电接触结构及其制造方法。 该制造包括例如提供设置在半导体衬底上的至少一个接触开口; 形成包含含碳物质和设置在其中的元素碳的富碳接触衬垫材料，所述含碳物质和所述元素碳一起限定所述富碳接触衬里材料内的固定碳含量; 以及将所述富碳接触衬垫材料共形地沉积在设置在所述半导体衬底上的所述至少一个接触开口内。

公开(公告)号：US20190228976A1

公开(公告)日：2019-07-25

申请号：US15876407

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Jinsheng GAO ,  Hong YU ,  Jinping LIU ,  Huang LIU

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.