公开(公告)号：US08735241B1

公开(公告)日：2014-05-27

申请号：US13747972

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Roman Boschke

IPC: H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

Abstract: Methods for forming CMOS integrated circuit structures are provided, the methods comprising performing a first implantation process for performing at least one of a halo implantation and a source and drain extension implantation into a region of a semiconductor substrate and then forming a stressor region in another region of the semiconductor substrate. Furthermore, a semiconductor device structure is provided, the structure comprising a stressor region embedded into a semiconductor substrate adjacent to a gate structure, the embedded stressor region having a surface differing along a normal direction of the surface from an interface by less than about 8 nm, wherein the interface is formed between the gate structure and the substrate.

Abstract translation: 提供了用于形成CMOS集成电路结构的方法，所述方法包括执行第一注入工艺，用于将光晕注入和源极和漏极延伸注入中的至少一个进行到半导体衬底的区域中，然后在另一区域中形成应力区域 的半导体衬底。 此外，提供了一种半导体器件结构，该结构包括嵌入到与栅极结构相邻的半导体衬底中的应力区域，所述嵌入的应力区域具有沿着表面的法线方向从界面相差小于约8nm的表面 其中所述界面形成在所述栅极结构和所述衬底之间。

公开(公告)号：US09515155B2

公开(公告)日：2016-12-06

申请号：US14136815

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62 ,  H01L23/525

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。

公开(公告)号：US09006835B2

公开(公告)日：2015-04-14

申请号：US14074905

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract translation: 半导体器件包括位于第一半导体区域中和上方的第一晶体管，所述第一半导体区域具有第一上表面并且包括第一半导体材料。 所述半导体器件还包括位于所述第一半导体区域的所述第一上表面上的第一突起漏极和源极部分，所述第一漏极和源极部分包括具有与所述第一半导体材料不同的材料组成的第二半导体材料。 此外，半导体器件包括位于第二半导体区域中和上方的第二晶体管，第二半导体区域包括第一半导体材料。 最后，半导体器件还包括嵌入在第二半导体区域中的应变诱导区域，包括第二半导体材料的嵌入的应变诱导区域。

公开(公告)号：US20150162414A1

公开(公告)日：2015-06-11

申请号：US14097338

申请日：2013-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Elke Erben

IPC: H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 所要求保护的方法提出了通过在金属栅极层和栅极半导体材料之间形成包括附加金属层的栅极结构而实现的改进的全硅化栅。 然后可以优化硅化工艺，以便形成包含附加金属层的金属和形成与下金属硅化物层的界面的上金属硅化物层的下金属硅化物层。

公开(公告)号：US20140131805A1

公开(公告)日：2014-05-15

申请号：US14074905

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract translation: 半导体器件包括位于第一半导体区域中和上方的第一晶体管，所述第一半导体区域具有第一上表面并且包括第一半导体材料。 所述半导体器件还包括位于所述第一半导体区域的所述第一上表面上的第一突起漏极和源极部分，所述第一漏极和源极部分包括具有与所述第一半导体材料不同的材料组成的第二半导体材料。 此外，半导体器件包括位于第二半导体区域中和上方的第二晶体管，第二半导体区域包括第一半导体材料。 最后，半导体器件还包括嵌入在第二半导体区域中的应变诱导区域，包括第二半导体材料的嵌入的应变诱导区域。

公开(公告)号：US20150179753A1

公开(公告)日：2015-06-25

申请号：US14136815

申请日：2013-12-20

Applicant: Globalfoundries Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。

公开(公告)号：US09431508B2

公开(公告)日：2016-08-30

申请号：US14047517

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Roman Boschke

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.

Abstract translation: 当根据栅极第一HKMG方法形成场效应晶体管时，形成在栅电极顶部上的覆盖层必须在硅化步骤之前去除，导致在栅电极的表面上形成金属硅化物层，并且 晶体管的源极和漏极区域。 本公开通过跳过栅极盖去除工艺来改善制造流程。 仅在源区和漏区形成金属硅化物。 然后通过形成通过栅极材料的孔而使栅电极接触，留下栅极金属层的表面。

公开(公告)号：US09236440B2

公开(公告)日：2016-01-12

申请号：US14097338

申请日：2013-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Elke Erben

IPC: H01L21/44 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 所要求保护的方法提出了通过在金属栅极层和栅极半导体材料之间形成包括附加金属层的栅极结构而实现的改进的全硅化栅。 然后可以优化硅化工艺，以便形成包含附加金属层的金属和形成与下金属硅化物层的界面的上金属硅化物层的下金属硅化物层。

公开(公告)号：US20150097252A1

公开(公告)日：2015-04-09

申请号：US14047517

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Roman Boschke

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.

Abstract translation: 当根据栅极第一HKMG方法形成场效应晶体管时，形成在栅电极顶部上的覆盖层必须在硅化步骤之前去除，导致在栅电极的表面上形成金属硅化物层，并且 晶体管的源极和漏极区域。 本公开通过跳过栅极盖去除工艺来改善制造流程。 仅在源区和漏区形成金属硅化物。 然后通过形成通过栅极材料的孔而使栅电极接触，留下栅极金属层的表面。

公开(公告)号：US08846467B1

公开(公告)日：2014-09-30

申请号：US14021525

申请日：2013-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823443

Abstract: A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.

Abstract translation: 提供了一种执行栅极电极的硅化的方法，其包括在同一半导体衬底上形成第一晶体管与由盖层覆盖的第一栅电极和半导体器件，在第一晶体管上形成有机平坦化层（OPL） 和半导体器件，背面蚀刻OPL使得OPL的上表面位于低于帽层的上表面的水平的水平，形成覆盖半导体器件而不覆盖第一晶体管的掩模层， 在存在反蚀刻的OPL和掩模层的同时移除盖层，并且执行第一栅电极的硅化。