公开(公告)号：US20180182708A1

公开(公告)日：2018-06-28

申请号：US15388530

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat AHMED ,  Benjamin G. MOSER ,  Vimal Kumar KAMINENI ,  Dinesh KOLI ,  Vishal CHHABRA

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/265 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/265 ,  H01L21/321 ,  H01L21/32139 ,  H01L21/76807 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.

公开(公告)号：US20190019862A1

公开(公告)日：2019-01-17

申请号：US15649294

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： A K M Zahidur Rahim CHOWDHURY ,  Shahrukh Akbar KHAN ,  Joseph SHEPARD, JR. ,  Mohammad HASANUZZAMAN ,  Naved A. SIDDIQUI ,  Shafaat AHMED

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/324

Abstract: Methods for preventing fin bending in FinFET devices and related devices are provided. Embodiments include forming fins in a substrate; forming a non-conformal sacrificial layer over and between the fins to structurally conjoin the fins or an array of fins for structural integrity; forming a first gap-fill dielectric over the sacrificial layer and fins; recessing the first gap-fill dielectric to expose an upper portion of the fins and sacrificial layer; etching the sacrificial layer to expose the fins; forming a second gap-fill dielectric over the first gap-fill dielectric and over and between the fins; and recessing the second gap-fill dielectric to expose the upper portion of the fins.

公开(公告)号：US20190206729A1

公开(公告)日：2019-07-04

申请号：US15860318

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang FANG ,  Shafaat AHMED ,  Zhiguo SUN ,  Jiehui SHU ,  Dinesh R. KOLI ,  Wei-Tsu TSENG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

公开(公告)号：US20180019162A1

公开(公告)日：2018-01-18

申请号：US15208852

申请日：2016-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shafaat AHMED ,  Shahrukh Akbar KHAN ,  Vishal CHHABRA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method of forming an amorphous carbon (aC) layer as a barrier layer for preventing etching of metals in a dual damascene metallization process and the resulting device are provided. Embodiments include forming an inter-layer dielectric (ILD) layer over a substrate with the first ILD having recesses for a first metallization layer. Then forming a TaN barrier layer and Co liner in the recesses, filling the recesses with a metal, forming a Co cap layer over the metal and forming a conformal aC layer over the substrate are accomplished. Furthermore, an Nblock layer, an ILD layer and a metal hard mask layer completes the stack on top to the aC layer. Subsequently, the embodiments include etching vias through this stack down to the aC layer, thereby protecting the first metallized layer.