公开(公告)号：US20180019162A1

公开(公告)日：2018-01-18

申请号：US15208852

申请日：2016-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shafaat AHMED ,  Shahrukh Akbar KHAN ,  Vishal CHHABRA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method of forming an amorphous carbon (aC) layer as a barrier layer for preventing etching of metals in a dual damascene metallization process and the resulting device are provided. Embodiments include forming an inter-layer dielectric (ILD) layer over a substrate with the first ILD having recesses for a first metallization layer. Then forming a TaN barrier layer and Co liner in the recesses, filling the recesses with a metal, forming a Co cap layer over the metal and forming a conformal aC layer over the substrate are accomplished. Furthermore, an Nblock layer, an ILD layer and a metal hard mask layer completes the stack on top to the aC layer. Subsequently, the embodiments include etching vias through this stack down to the aC layer, thereby protecting the first metallized layer.

公开(公告)号：US20180182708A1

公开(公告)日：2018-06-28

申请号：US15388530

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat AHMED ,  Benjamin G. MOSER ,  Vimal Kumar KAMINENI ,  Dinesh KOLI ,  Vishal CHHABRA

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/265 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/265 ,  H01L21/321 ,  H01L21/32139 ,  H01L21/76807 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.

公开(公告)号：US20190393221A1

公开(公告)日：2019-12-26

申请号：US16562481

申请日：2019-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Ayse M. OZBEK ,  Tao CHU ,  Bala HARAN ,  Vishal CHHABRA ,  Katsunori ONISHI ,  Guowei XU

IPC: H01L27/092 ,  H01L21/027 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L27/02 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US20190115346A1

公开(公告)日：2019-04-18

申请号：US15783549

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Ayse M. OZBEK ,  Tao CHU ,  Bala HARAN ,  Vishal CHHABRA ,  Katsunori ONISHI ,  Guowei XU

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.