-
公开(公告)号：US09842844B2
公开(公告)日：2017-12-12
申请号：US14491981
申请日：2014-09-20
发明人： Ling Wu , Jianbo Yang , Kian Hong Lim , Sung Mun Jung
IPC分类号： H01L27/112 , H01L27/115 , H01L29/788 , H01L21/28 , H01L27/11521 , H01L29/06 , H01L27/11548 , H01L21/768 , H01L29/423 , H01L27/11526
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76802 , H01L27/11526 , H01L27/11548 , H01L29/0619 , H01L29/42324 , H01L29/42328 , H01L29/788
摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.
-
公开(公告)号：US09269766B2
公开(公告)日：2016-02-23
申请号：US14490629
申请日：2014-09-18
发明人： Ling Wu , Jianbo Yang , Kian Hong Lim , Sung Mun Jung
IPC分类号： H01L27/00 , H01L29/06 , H01L27/115 , H01L21/28 , H01L21/768 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76802 , H01L27/11526 , H01L27/11548 , H01L29/0619 , H01L29/42324 , H01L29/42328 , H01L29/788
摘要： A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.
摘要翻译： 提出了一种用于形成装置的装置和方法。 该方法包括提供具有其中将形成存储器单元的阵列区域的衬底。 存储单元的存储门形成在阵列区域中。 形成围绕阵列区域的保护环。 在基板上形成栅电极层。 栅极电极层填充存储栅极和保护环之间的间隙。 栅电极层被平坦化以在栅电极层，存储门和保护环之间产生平面。 保护环保持阵列区域中的栅电极层的厚度，使得跨阵列区域的中心和边缘区域的存储栅的厚度是均匀的。
-
3.发明授权公开(公告)号：US09054135B2
公开(公告)日：2015-06-09
申请号：US13955637
申请日：2013-07-31
发明人： Bing Li , Sung Mun Jung , Yi Tat Lim
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L27/11534 , H01L21/823418 , H01L27/11546 , H01L29/66492 , H01L29/66825 , H01L29/7881
摘要： Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.
摘要翻译： 公开了用于制造集成电路的方法。 在示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成硅材料层。 该方法还包括在硅材料层上并在存储器栅叠层上方形成覆盖层，从存储器阵列区域和高压MOSFET区域上方去除覆盖层，在覆盖层上形成第二硅材料层 第一硅材料层，以及去除第二硅材料层。 该方法还包括从逻辑器件区域中的第一硅材料层上方去除覆盖层，并且从高压MOSFET区域去除第一和第二硅材料层。 此外，该方法包括在存储器阵列区域和逻辑器件区域上形成光致抗蚀剂材料层，并将半导体衬底暴露于离子注入工艺。
-
公开(公告)号：US09431408B2
公开(公告)日：2016-08-30
申请号：US14705751
申请日：2015-05-06
发明人： Bing Li , Sung Mun Jung , Yi Tat Lim
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66
CPC分类号： H01L27/11534 , H01L21/823418 , H01L27/11546 , H01L29/66492 , H01L29/66825 , H01L29/7881
摘要： Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.
-
公开(公告)号：US09406687B1
公开(公告)日：2016-08-02
申请号：US14664940
申请日：2015-03-23
发明人： Jianbo Yang , Yi Tat Lim , Sung Mun Jung
IPC分类号： H01L27/115 , H01L29/788 , H01L29/66 , H01L29/423 , H01L21/28
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11529 , H01L27/11531 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： Device and method for forming a device are presented. The method includes providing a substrate prepared with at least a memory cell region having first and second sub-regions and a logic region having input/output (I/O) region and core region. First voltage memory cell is formed in the first sub-region and second voltage memory cell is formed in the second sub-region of the memory cell region of the same substrate. The first voltage memory cell operates in a first voltage and the second voltage memory cell operates in a second voltage which is higher than the first voltage. Each of the first and second voltage memory cells includes a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Logic I/O device is formed in the I/O region and logic core device is formed in the core region.
摘要翻译： 提出了用于形成装置的装置和方法。 该方法包括提供至少具有第一和第二子区域的存储单元区域以及具有输入/输出（I / O）区域和核心区域的逻辑区域的衬底。 第一电压存储单元形成在第一子区域中，第二电压存储单元形成在同一衬底的存储单元区域的第二子区域中。 第一电压存储单元以第一电压工作，而第二电压存储单元以高于第一电压的第二电压工作。 第一和第二电压存储单元中的每一个包括具有第一和第二门的分离门。 第一栅极是在浮动栅极上具有控制栅极的存储栅极，第二栅极是字线。 逻辑I / O设备形成在I / O区域中，并且在核心区域中形成逻辑核心设备。
-
公开(公告)号：US20150236032A1
公开(公告)日：2015-08-20
申请号：US14705751
申请日：2015-05-06
发明人： Bing Li , Sung Mun Jung , Yi Tat Lim
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L27/11534 , H01L21/823418 , H01L27/11546 , H01L29/66492 , H01L29/66825 , H01L29/7881
摘要： Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.
-
公开(公告)号：US09911665B2
公开(公告)日：2018-03-06
申请号：US14586466
申请日：2014-12-30
发明人： Wenhu Liu , Sung Mun Jung , Yi Tat Lim , Ling Wu
IPC分类号： H01L29/423 , H01L21/66 , H01L29/66 , H01L29/788
CPC分类号： H01L22/14 , H01L22/34 , H01L29/66825 , H01L29/7881
摘要： Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an STI structure disposed therein, adjacent to the active region. A first gate electrode structure overlies the active region and includes a first gate dielectric layer and a first gate electrode layer. A second gate electrode structure includes a second gate dielectric layer that overlies the first gate electrode layer and a second gate electrode layer that overlies the second gate dielectric layer. A source and drain region are formed in the active region, adjacent to the first gate electrode structure. First electrical interconnects are in electrical communication with the source and drain regions. A second electrical interconnect is in electrical communication with the first gate electrode layer.
-
公开(公告)号：US08664708B2
公开(公告)日：2014-03-04
申请号：US13775259
申请日：2013-02-25
发明人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
摘要翻译： 公开了一种形成装置的方法。 该方法包括提供准备有单元区域的基板，并在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括围绕第一子栅极的第二子栅极。 第一栅极的第一和第二子栅极由第一栅极介电层分开。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 该方法还包括形成第一和第二晶体管的第一和第二结。 第一栅极端子形成并耦合到第一晶体管的第二子栅极。 第二栅极端子形成并耦合到至少第二晶体管的第一子栅极。
-
公开(公告)号：US10170437B1
公开(公告)日：2019-01-01
申请号：US15714503
申请日：2017-09-25
发明人： Ramasamy Chockalingam , Juan Boon Tan , Sung Mun Jung , Wenhu Liu , Ee Jan Khor
IPC分类号： H01L23/00 , H01L21/311 , H01L23/528 , H01L23/532 , H01L21/768 , H01L23/522
摘要： A method of forming a stop layer to prevent dummy vias from connecting to a metal layer and the resulting device are provided. Embodiments include forming a first metal layer in a first dielectric layer; forming a second dielectric layer over a first Nblok layer formed over the first dielectric and first metal layers; forming a third dielectric layer over the second dielectric layer and a second Nblok layer formed over a portion of the second dielectric layer; forming a via and a plurality of vias through the third and second dielectric layers down to the second and first Nblok layers, respectively; removing portions of the second and first Nblok layers through the via and the plurality of vias down to the second dielectric layer and the first metal layer, respectively; removing portions of the third dielectric layer through each via; and filling each via with a second metal layer.
-
公开(公告)号：US09960172B2
公开(公告)日：2018-05-01
申请号：US14547155
申请日：2014-11-19
发明人： Jianbo Yang , Ling Wu , Sung Mun Jung
IPC分类号： H01L29/788 , H01L27/11521 , H01L29/423 , H01L29/66 , H01L21/28 , H01L21/265
CPC分类号： H01L27/11521 , H01L21/26513 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.015 秒)
