公开(公告)号：US11257718B2

公开(公告)日：2022-02-22

申请号：US16780046

申请日：2020-02-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Chanro Park ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/088 ,  H01L29/45 ,  H01L29/06 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

公开(公告)号：US10923389B2

公开(公告)日：2021-02-16

申请号：US16288780

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10903317B1

公开(公告)日：2021-01-26

申请号：US16534317

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US11380581B2

公开(公告)日：2022-07-05

申请号：US16185015

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Andre P. Labonte ,  Catherine B Labelle ,  Chanro Park

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

Abstract: A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.

公开(公告)号：US20240339538A1

公开(公告)日：2024-10-10

申请号：US18749813

申请日：2024-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

公开(公告)号：US12094972B2

公开(公告)日：2024-09-17

申请号：US16406071

申请日：2019-05-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.