公开(公告)号：US11908917B2

公开(公告)日：2024-02-20

申请号：US17404499

申请日：2021-08-17

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4983 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/66795

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

公开(公告)号：US11522068B2

公开(公告)日：2022-12-06

申请号：US16523340

申请日：2019-07-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/84

Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

公开(公告)号：US11349028B2

公开(公告)日：2022-05-31

申请号：US16568242

申请日：2019-09-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49

Abstract: A semiconductor device comprising a substrate with a first fin and a second fin disposed on the substrate. A gate electrode is over the first fin and the second fin. A gate-cut pedestal is positioned between the first fin and the second fin, the gate-cut pedestal having side surfaces and a top surface. A portion of the side surfaces of the gate-cut pedestal is covered by the gate electrode. The gate-cut pedestal has a height that is substantially similar to a height of the first fin or the second fin.

公开(公告)号：US11075298B2

公开(公告)日：2021-07-27

申请号：US16454238

申请日：2019-06-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Judson R. Holt ,  Sipeng Gu ,  Halting Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/417

Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.

公开(公告)号：US11031389B2

公开(公告)日：2021-06-08

申请号：US16436925

申请日：2019-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L27/06 ,  H01L27/105 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to semiconductor structures disposed over active regions, more particularly, via contact structures disposed over such active regions and to methods of forming such semiconductor structures.

公开(公告)号：US11349030B2

公开(公告)日：2022-05-31

申请号：US16739299

申请日：2020-01-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Haiting Wang ,  Hong Yu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.

公开(公告)号：US11348870B2

公开(公告)日：2022-05-31

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US11264382B2

公开(公告)日：2022-03-01

申请号：US16942816

申请日：2020-07-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jiehui Shu ,  Bharat V. Krishnan

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

公开(公告)号：US11114466B2

公开(公告)日：2021-09-07

申请号：US16774087

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/306 ,  H01L21/84 ,  H01L21/265 ,  H01L21/76

Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

公开(公告)号：US11004953B2

公开(公告)日：2021-05-11

申请号：US16454016

申请日：2019-06-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Rinus Tek Po Lee ,  Hui Zang ,  Jiehui Shu ,  Hong Yu ,  Wei Hong

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer.