公开(公告)号：US20240186429A1

公开(公告)日：2024-06-06

申请号：US18062201

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: H01L31/0224 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/022408 ,  H01L31/03125 ,  H01L31/1037 ,  H01L31/1812

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode includes a transfer gate and a floating diffusion adjacent to the transfer gate. In addition, the photodiode includes an upper terminal; an intrinsic semiconductor region in contact with the upper terminal, the intrinsic semiconductor region in a trench in a substrate adjacent to the transfer gate; and a lower terminal in contact with the intrinsic semiconductor region. An insulator layer is along an entirety of a sidewall of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well may also optionally be between the insulator layer and the transfer gate.

公开(公告)号：US11777043B1

公开(公告)日：2023-10-03

申请号：US17807887

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey M. Hazbun ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Siva P. Adusumilli

IPC: H01L31/0352

CPC classification number: H01L31/035281

Abstract: A substrate is formed to include a substrate base and a substrate extension. A photodiode contacts the substrate base. The substrate extension is adjacent the photodiode. An additional device contacts the substrate extension. A sidewall spacer contacts the photodiode and the substrate extension. The additional device includes conductive elements within the substrate extension adjacent the sidewall spacer.

公开(公告)号：US20230417695A1

公开(公告)日：2023-12-28

申请号：US17808176

申请日：2022-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Ramsey M. Hazbun ,  John J. Ellis-Monaghan

IPC: G01N27/06 ,  H01L31/105 ,  H01L31/0352 ,  H01L31/18

CPC classification number: G01N27/06 ,  H01L31/105 ,  H01L31/035209 ,  H01L31/1804

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

公开(公告)号：US20230139011A1

公开(公告)日：2023-05-04

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US12281996B2

公开(公告)日：2025-04-22

申请号：US17808176

申请日：2022-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Ramsey M. Hazbun ,  John J. Ellis-Monaghan

IPC: G01N27/06 ,  H10F30/223 ,  H10F71/00 ,  H10F77/14

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

公开(公告)号：US20230405582A1

公开(公告)日：2023-12-21

申请号：US17807896

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Ramsey M. Hazbun ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: B01L3/00 ,  G01N27/414

CPC classification number: B01L3/502715 ,  B01L2200/12 ,  G01N27/414 ,  B01L3/502707

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

公开(公告)号：US20230034728A1

公开(公告)日：2023-02-02

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US12062574B2

公开(公告)日：2024-08-13

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US20240125732A1

公开(公告)日：2024-04-18

申请号：US18047405

申请日：2022-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Mark D. Levy ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: G01N27/414

CPC classification number: G01N27/414

Abstract: A structure includes a cavity in a semiconductor substrate; a field effect transistor positioned over the cavity; an opening in the semiconductor substrate extending to the cavity; and a layer of insulating material filling the opening and forming an insulating material window to the cavity.

公开(公告)号：US11916119B2

公开(公告)日：2024-02-27

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/41783 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/7786

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.