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    High voltage input buffer made by a low voltage process and having a self-adjusting trigger point
    4.
    发明授权
    High voltage input buffer made by a low voltage process and having a self-adjusting trigger point 有权
    高电压输入缓冲器由低电压工艺制成，具有自调节触发点

    公开(公告)号：US06288599B1

    公开(公告)日：2001-09-11

    申请号：US09634561

    申请日：2000-08-09

    申请人： John Deane Coddington

    发明人： John Deane Coddington

    IPC分类号： H02J338

    CPC分类号： H03K19/0027 ,  H03K19/018585

    摘要： A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

    摘要翻译： 使用低电压工艺的高性能高输入电压输入缓冲器制造包含输入缓冲电路（136）和电平转换器（132）。 输入缓冲器（136）将通过芯片焊盘（112）接收输入信号。 来自跳闸焊盘（112）的输入信号将被提供给包含或耦合到保护晶体管（116,114,110和111）的反相器堆叠（135）。 保护晶体管被参考发生器（134）偏置，该参考发生器输出作为可提供在芯片焊盘（112）上的最大电压的函数的电压。 通过使用电路（134），可以针对任何OVDD（110）值动态地调整反相器堆叠（135）的触发点，由此提高输入缓冲器性能并使其变得更加灵活。

    Output buffer
    5.
    发明授权
    Output buffer 有权
    输出缓冲区

    公开(公告)号：US06169420A

    公开(公告)日：2001-01-02

    申请号：US09131515

    申请日：1998-08-10

    申请人： John Deane Coddington ,  Perry H. Pelley, III

    发明人： John Deane Coddington ,  Perry H. Pelley, III

    IPC分类号： H03K190175

    CPC分类号： H03K19/00315

    摘要： An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

    摘要翻译： 一种具有保护电路（228,230,232）的输出缓冲器（200），其响应于输出引脚（202）上的外部电压来调节对输出驱动电路（224,226）的控制。 当输出引脚处于三态状态并接收超出预定电压范围的外部电压时，保护电路调节输出驱动电路中的晶体管（224）的控制栅上的电压。 保护电路将晶体管两端的电压保持在晶体管的容限内。 在一个实施例中，输出驱动电路具有上拉（204）和下拉（206）部分。 输出缓冲器提供具有低电压器件的高电压输出驱动器。

    System with DLL
    6.
    发明授权
    System with DLL 失效
    系统与DLL

    公开(公告)号：US6140854A

    公开(公告)日：2000-10-31

    申请号：US236775

    申请日：1999-01-25

    申请人： John Deane Coddington ,  Chau-Shing Hui

    发明人： John Deane Coddington ,  Chau-Shing Hui

    IPC分类号： G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/07 ,  H03L7/089

    摘要： A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

    摘要翻译： 系统（50）具有移位延迟电路（60），其提供用于延迟源时钟的可变延迟和延迟锁定环（DLL）（70），延迟锁定环（DLL）（70）包括延迟线（72），延迟线（72）提供可变延迟以延迟 源时钟。 延迟线（18）具有由计数器（74）变化的延迟。 计数器（74）增加以改变延迟。 移位延迟电路（60）基于与源时钟具有已知关系的参考时钟（GCLK）的半周期。 源时钟的总延迟是通过移位延迟电路（60）和延迟线（72）提供的总延迟的组合。 由于使用了移位延迟电路（60），因此在集成电路中需要较大量的管芯面积的延迟线（72）的尺寸可以更小。

    System with DLL
    7.
    发明授权
    System with DLL 有权
    系统与DLL

    公开(公告)号：US06294938B1

    公开(公告)日：2001-09-25

    申请号：US09552824

    申请日：2000-04-20

    申请人： John Deane Coddington ,  Chau-Shing Hui

    发明人： John Deane Coddington ,  Chau-Shing Hui

    IPC分类号： H03L706

    CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/07 ,  H03L7/089

    摘要： A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

    摘要翻译： 系统（50）具有移位延迟电路（60），其提供用于延迟源时钟的可变延迟和延迟锁定环（DLL）（70），延迟锁定环（DLL）（70）包括延迟线（72），延迟线（72）提供可变延迟以延迟 源时钟。 延迟线（18）具有由计数器（74）变化的延迟。 计数器（74）增加以改变延迟。 移位延迟电路（60）基于与源时钟具有已知关系的参考时钟（GCLK）的半周期。 源时钟的总延迟是通过移位延迟电路（60）和延迟线（72）提供的总延迟的组合。 由于使用了移位延迟电路（60），因此在集成电路中需要较大量的管芯面积的延迟线（72）的尺寸可以更小。

    High voltage input buffer made by a low voltage process and having a self-adjusting trigger point
    8.
    发明授权
    High voltage input buffer made by a low voltage process and having a self-adjusting trigger point 失效

    公开(公告)号：US6147540A

    公开(公告)日：2000-11-14

    申请号：US143844

    申请日：1998-08-31

    申请人： John Deane Coddington

    发明人： John Deane Coddington

    IPC分类号： H03K19/0175 ,  H03K19/00 ,  H03K19/0185 ,  H03L5/00

    CPC分类号： H03K19/0027 ,  H03K19/018585

    摘要： A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

    High voltage input buffer made by a low voltage process and having a self-adjusting trigger point
    9.
    发明授权
    High voltage input buffer made by a low voltage process and having a self-adjusting trigger point 有权
    高电压输入缓冲器由低电压工艺制成，具有自调节触发点

    公开(公告)号：US06346829B1

    公开(公告)日：2002-02-12

    申请号：US09634921

    申请日：2000-08-09

    申请人： John Deane Coddington

    发明人： John Deane Coddington

    IPC分类号： H03K190175

    CPC分类号： H03K19/0027 ,  H03K19/018585

    摘要： A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

    摘要翻译： 使用低电压工艺的高性能高输入电压输入缓冲器制造包含输入缓冲电路（136）和电平转换器（132）。 输入缓冲器（136）将通过芯片焊盘（112）接收输入信号。 来自跳闸焊盘（112）的输入信号将被提供给包含或耦合到保护晶体管（116,114,110和111）的反相器堆叠（135）。 保护晶体管被参考发生器（134）偏置，该参考发生器输出作为可提供在芯片焊盘（112）上的最大电压的函数的电压。 通过使用电路（134），可以针对任何OVDD（110）值动态地调整反相器堆叠（135）的触发点，由此提高输入缓冲器性能并使其变得更加灵活。

    Output buffer and method therefor
    10.
    发明授权
    Output buffer and method therefor 有权
    输出缓冲器及其方法

    公开(公告)号：US06326811B1

    公开(公告)日：2001-12-04

    申请号：US09659400

    申请日：2000-09-11

    申请人： John Deane Coddington ,  Perry H. Pelley III

    发明人： John Deane Coddington ,  Perry H. Pelley III

    IPC分类号： H03K19003

    CPC分类号： H03K19/00315

    摘要： An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224, 226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

    摘要翻译： 一种具有保护电路（228,230,232）的输出缓冲器（200），其响应于输出引脚（202）上的外部电压调节对输出驱动电路（224,226）的控制。 当输出引脚处于三态状态并接收超出预定电压范围的外部电压时，保护电路调节输出驱动电路中的晶体管（224）的控制栅上的电压。 保护电路将晶体管两端的电压保持在晶体管的容限内。 在一个实施例中，输出驱动电路具有上拉（204）和下拉（206）部分。 输出缓冲器提供具有低电压器件的高电压输出驱动器。