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公开(公告)号：US6115502A
公开(公告)日：2000-09-05
申请号：US950562
申请日：1997-10-15
申请人： Gerard De Haan , Pieter J. Snijder
发明人： Gerard De Haan , Pieter J. Snijder
摘要： In a motion-dependent noise filtering (MD, NRF), a received image signal and a delayed (3) image signal are combined in dependence upon both a local amount of motion and a global amount of motion in the image signals.
摘要翻译： 在运动相关噪声滤波（MD，NRF）中，接收的图像信号和延迟的（3）图像信号根据图像信号中的局部运动量和全局运动量两者来组合。
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公开(公告)号：US4280068A
公开(公告)日：1981-07-21
申请号：US154252
申请日：1980-05-29
申请人： Pieter J. Snijder
发明人： Pieter J. Snijder
IPC分类号： H01L29/762 , H01L21/339 , H01L27/14 , H01L29/10 , H01L29/768 , G11C19/28 , H01L29/78
CPC分类号： H01L29/76808 , H01L29/1062
摘要： In bulk channel charge coupled devices the nonlinearity in the input characteristic caused by varactor effects is removed by moving the potential well in which the charge packets are generated below the input electrode to the surface where the center of electrical charge is substantially independent of the value of the charge. Said shift can be obtained by external means, for example an extra d.c. voltage at the input electrode, or by internal means, for example a thicker oxide below the input electrode.
摘要翻译： 在体通道电荷耦合器件中，由变容二极管效应引起的输入特性中的非线性通过将电荷阱在输入电极下方产生的电势阱移动到电荷中心基本上与 费用。 所述偏移可以通过外部手段获得，例如额外的直流 输入电极处的电压，或通过内部装置，例如输入电极下方较厚的氧化物。
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公开(公告)号：US20100238637A1
公开(公告)日：2010-09-23
申请号：US12303572
申请日：2007-06-05
IPC分类号： H05K7/02
CPC分类号： H05K3/301 , H05K1/038 , H05K3/308 , H05K3/321 , H05K2201/029 , H05K2201/10106 , H05K2201/10325 , H05K2201/10651 , H05K2201/10818 , H05K2201/10825 , H05K2201/10962 , H05K2201/209 , H05K2203/1446
摘要： A submount for arranging electronic components on a substrate is provided. The submount comprises a head member and at least one substrate-engaging member protruding from the head member. The head member comprises at least two, from each other isolated, electrically conductive portions, where each electrically conductive portion comprises a component contact, adapted for connection of electronic components thereto, and a substrate contact on arranged on said substrate side, adapted for bringing said electrically conductive portions in contact with a circuitry comprised in said substrate. The submount of the present invention may be used to attach electronic components, such as light-emitting diodes, to a textile substrate, without the need for soldering the electronic component directly on the substrate.
摘要翻译： 提供了一种用于在基板上布置电子部件的基座。 底座包括头部构件和从头部构件突出的至少一个衬底接合构件。 头部构件包括彼此隔离的导电部分中的至少两个，其中每个导电部分包括适于将电子部件连接到其上的部件接触件和布置在所述基板侧上的基板接触件，适于使所述 与包括在所述衬底中的电路接触的导电部分。 本发明的基座可以用于将诸如发光二极管的电子部件附接到纺织品基板，而不需要将电子部件直接焊接在基板上。
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4.发明授权System and method for dynamically calibrating driver circuits in a display device 有权用于在显示装置中动态校准驱动电路的系统和方法公开(公告)号：US07872626B2
公开(公告)日：2011-01-18
申请号：US10563847
申请日：2004-06-30
申请人： Adrianus Sempel , Pieter J. Snijder
发明人： Adrianus Sempel , Pieter J. Snijder
CPC分类号： G09G3/3216 , G09G3/3225 , G09G3/3283 , G09G3/3685 , G09G2320/0233 , G09G2320/0693
摘要： A display device has an array of display elements (2) each driven by an input provided on a data conductor (6). These inputs are generated by data conductor addressing circuitry (9) which has a plurality of controllable driver circuits (32,34,40), each for providing an input to an associated data conductor. The number of controllable driver circuits is at least one greater than the number required for providing data to all data conductors. A reference driver circuit (30) is used for calibrating at least one of the controllable driver circuits whilst the other controllable driver circuits provide inputs to the data conductors. This provides a reduction in the spread of driver circuit outputs by calibration of the driver circuits using a reference driver circuit.
摘要翻译： 显示装置具有由数据导体（6）上提供的输入驱动的显示元件阵列（2）。 这些输入由具有多个可控驱动器电路（32,34,40）的数据导体寻址电路（9）产生，每个用于向相关联的数据导体提供输入。 可控制驱动器电路的数量至少大于向所有数据导体提供数据所需的数量。 参考驱动器电路（30）用于校准可控驱动器电路中的至少一个，而其他可控驱动器电路为数据导体提供输入。 这通过使用参考驱动器电路校准驱动器电路来降低驱动器电路输出的扩展。
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公开(公告)号：US4918402A
公开(公告)日：1990-04-17
申请号：US314294
申请日：1989-02-22
摘要： A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, between the second inputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) and a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.12), a fifth capacitor (C5) is arranged between the second inputs (26,28) of the second transconductor (G.sub.11) and the fourth transconductor (G.sub.13), and a sixth capacitor (C6) is arranged between the second inputs (25,28) of the first transconductor (G.sub.10) and the fourth transconductor (G.sub.13). The third (C3), fourth (C4) and sixth (C6) capacitors reduce resonance tendencies of the circuit and consequent resonance rise symptoms as a result of parasitic effects.
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公开(公告)号：US4853651A
公开(公告)日：1989-08-01
申请号：US94471
申请日：1987-09-08
摘要： A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, while between the second imputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.12), a fifth capacitor (C5) is arranged between the second inputs (26,28) of the second transconductor (G.sub.11) and the fourth transconductor (G.sub.13), and a sixth capacitor (C6) is arranged between the second inputs (25,28) of the first transconductor (G.sub.10) and the fourth transconductor (G.sub.13). The third (C3), fourth (C4) and sixth (C6) capacitors reduce resonance tendencies of the circuit and consequent resonant rise symptoms as a result of parasitic effects.
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