利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

134 条记录 (耗时 0.02 秒)

    Semiconductor device having a reduced signal processing time and a method of fabricating the same
    4.
    发明授权
    Semiconductor device having a reduced signal processing time and a method of fabricating the same 有权
    具有减小的信号处理时间的半导体器件及其制造方法

    公开(公告)号：US06541863B1

    公开(公告)日：2003-04-01

    申请号：US09475572

    申请日：2000-01-05

    申请人： Manfred Horstmann ,  Karsten Wieczorek ,  Gert Burbach

    发明人： Manfred Horstmann ,  Karsten Wieczorek ,  Gert Burbach

    IPC分类号： H01L2348

    CPC分类号： H01L23/5222 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

    摘要翻译： 提供了一种包括部分由多孔材料形成的绝缘层的半导体器件及其制造方法。 通过减少材料的量，即通过在金属化层的绝缘层中使用多孔材料，相当布线的杂散电容显着降低。 在一个实施例中，多孔层可以分开制造在另一个衬底上，随后转移到产品晶片，同时另外的衬底和产品晶片彼此适当地对准。 以这种方式，可以预先制造具有降低的介电常数的完整金属化层或与携带MOS结构的产品晶片同时进行。 由于金属化层的布线的电容降低，提高了集成电路的信号性能和/或功耗。

    Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
    6.
    发明授权
    Method of forming different silicide portions on different silicon-containing regions in a semiconductor device 有权
    在半导体器件中在不同含硅区域上形成不同硅化物部分的方法

    公开(公告)号：US07226859B2

    公开(公告)日：2007-06-05

    申请号：US10282720

    申请日：2002-10-29

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L29/40

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933

    摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

    摘要翻译： 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着提高单个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

    Field effect transistor with reduced gate delay and method of fabricating the same
    7.
    发明授权
    Field effect transistor with reduced gate delay and method of fabricating the same 有权
    具有减小的栅极延迟的场效应晶体管及其制造方法

    公开(公告)号：US06798028B2

    公开(公告)日：2004-09-28

    申请号：US09847622

    申请日：2001-05-02

    申请人： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    发明人： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    IPC分类号： H01L2976

    CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

    摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

    摘要翻译： 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。

    Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same
    8.
    发明授权
    Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same 有权
    在沟道区域具有逆向掺杂剂分布的半导体器件及其制造方法

    公开(公告)号：US06881641B2

    公开(公告)日：2005-04-19

    申请号：US10282980

    申请日：2002-10-29

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/331

    CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/6659

    摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

    摘要翻译： 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

    Method for fully self-aligned FET technology
    10.
    发明授权
    Method for fully self-aligned FET technology 有权
    完全自对准FET技术的方法

    公开(公告)号：US06492210B2

    公开(公告)日：2002-12-10

    申请号：US09810771

    申请日：2001-03-16

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan ,  Michael Raab

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan ,  Michael Raab

    IPC分类号： H01L2100

    CPC分类号： H01L29/66772 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78621

    摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

    摘要翻译： 本发明提供了在基于用于形成器件隔离特征和源极和漏极区域的栅电极和侧壁间隔物屏蔽程序的基础上使用自对准技术在集成电路中形成场效应晶体管的方法。 本发明能够增加半导体器件的积分密度，使场效应晶体管器件中的寄生电容最小化，以及更快的制造工艺。