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    Constructing a Clock Tree for an Integrated Circuit Design
    1.
    发明申请
    Constructing a Clock Tree for an Integrated Circuit Design 有权
    构建集成电路设计的时钟树

    公开(公告)号：US20120159416A1

    公开(公告)日：2012-06-21

    申请号：US13325102

    申请日：2011-12-14

    申请人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    发明人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/62

    摘要： A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

    摘要翻译： 公开了一种用于构建用于集成电路设计的时钟树的方法和装置，所述方法包括：通过对放置的网表执行定时分析来提取放置的网表中的顺序设备之间的路径延迟; 以及根据所述顺序设备之间的路径延迟构建用于驱动所述顺序设备的时钟树，以使得任何两个顺序设备之间的定时延迟的乘积和所述两个顺序设备的时钟树分支权重之和最小， 其中两个顺序设备的时钟树分支权重与从时钟树分支点相对于两个顺序设备到两个顺序设备的时钟树电平的数量正相关。

    Constructing a clock tree for an integrated circuit design
    2.
    发明授权
    Constructing a clock tree for an integrated circuit design 有权
    构建集成电路设计的时钟树

    公开(公告)号：US08484604B2

    公开(公告)日：2013-07-09

    申请号：US13325102

    申请日：2011-12-14

    申请人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    发明人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/62

    摘要： A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

    摘要翻译： 公开了一种用于构建用于集成电路设计的时钟树的方法和装置，所述方法包括：通过对放置的网表执行定时分析来提取放置的网表中的顺序设备之间的路径延迟; 以及根据所述顺序设备之间的路径延迟构建用于驱动所述顺序设备的时钟树，以使得任何两个顺序设备之间的定时延迟的乘积和所述两个顺序设备的时钟树分支权重之和最小， 其中两个顺序设备的时钟树分支权重与从时钟树分支点相对于两个顺序设备到两个顺序设备的时钟树电平的数量正相关。

    Frame boundary detection and synchronization system for data stream received by ethernet forward error correction layer
    3.
    发明授权
    Frame boundary detection and synchronization system for data stream received by ethernet forward error correction layer 失效
    通过以太网前向纠错层接收的数据流的帧边界检测和同步系统

    公开(公告)号：US08667373B2

    公开(公告)日：2014-03-04

    申请号：US12894274

    申请日：2010-09-30

    申请人： Yin He ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    发明人： Yin He ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0047 ,  H03M13/159 ,  H03M13/33 ,  H03M13/333 ,  H03M13/6561 ,  H04L7/048

    摘要： The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

    摘要翻译： 本发明公开了一种用于由以太网前向纠错层接收的数据流的帧边界检测系统和同步系统。 帧边界检测系统包括移位器，两个解扰器，综合征发生器和捕捉器。 误差捕获器包括一个大小端模式控制器，用于控制误差捕获器的大小端位转换。 如果错误捕获器以大端模式工作，则误差捕获器实现校正子发生器的功能，同时与校正子发生器一起工作，并执行第二个FEC校验，其中当移位器通过拦截数据执行FEC检查 长度为一帧加A位，可以验证帧的两个起始位置，其中A是小于一帧长度的正整数。 本发明可以提高帧边界检测速度和帧同步速度，并且仅增加少量的硬件开销。

    Frame Boundary Detection and Synchronization System for Data Stream Received by Ethernet Forward Error Correction Layer
    6.
    发明申请
    Frame Boundary Detection and Synchronization System for Data Stream Received by Ethernet Forward Error Correction Layer 失效
    通过以太网前向纠错层接收的数据流的帧边界检测和同步系统

    公开(公告)号：US20110078545A1

    公开(公告)日：2011-03-31

    申请号：US12894274

    申请日：2010-09-30

    申请人： Yin He ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    发明人： Yin He ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

    IPC分类号： H03M13/15 ,  G06F11/10

    CPC分类号： H04L1/0047 ,  H03M13/159 ,  H03M13/33 ,  H03M13/333 ,  H03M13/6561 ,  H04L7/048

    摘要： The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

    摘要翻译： 本发明公开了一种用于由以太网前向纠错层接收的数据流的帧边界检测系统和同步系统。 帧边界检测系统包括移位器，两个解扰器，综合征发生器和捕捉器。 误差捕获器包括一个大小端模式控制器，用于控制误差捕获器的大小端位转换。 如果错误捕获器以大端模式工作，则误差捕获器实现校正子发生器的功能，同时与校正子发生器一起工作，并执行第二个FEC校验，其中当移位器通过截取数据执行FEC检查 长度为一帧加A位，可以验证帧的两个起始位置，其中A是小于一帧长度的正整数。 本发明可以提高帧边界检测速度和帧同步速度，并且仅增加少量的硬件开销。

    Fabric able to form electronic element
    7.
    发明授权
    Fabric able to form electronic element 有权

    公开(公告)号：US10290444B2

    公开(公告)日：2019-05-14

    申请号：US12676549

    申请日：2008-09-03

    申请人： Changming Yang ,  Tzulin Yang ,  Chingwen Yang ,  Hao Yang

    发明人： Changming Yang ,  Tzulin Yang ,  Chingwen Yang ,  Hao Yang

    IPC分类号： H01C10/10 ,  H01C10/12 ,  H01H13/704

    摘要： A cloth material that can form an electronic component includes a cloth material layer, which includes at least one crevice; and a conductive area included in the cloth material layer, wherein a shape of the crevice and a shape of the conductive area change with an outside force. A cloth material that can form an electronic component includes two cloth material layers stacked to form a crevice therebetween; and a conductive area located on the two cloth material layers spanning from one side of the crevice to the other side of the crevice, wherein a shape of the crevice and the conductive area changes with an outside force.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09202937B2

    公开(公告)日：2015-12-01

    申请号：US13321960

    申请日：2010-05-14

    申请人： Alexander Dietrich Hölke ,  Deb Kumar Pal ,  Kia Yaw Kee ,  Hao Yang

    发明人： Alexander Dietrich Hölke ,  Deb Kumar Pal ,  Kia Yaw Kee ,  Hao Yang

    IPC分类号： H01L29/861 ,  H01L29/40

    CPC分类号： H01L29/868 ,  H01L29/405 ,  H01L29/407 ,  H01L29/8611

    摘要： A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.

    摘要翻译： 一种半导体器件，包括：p或p +掺杂部分; 通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分; 在所述漂移部分和所述至少一个掺杂部分相遇的区域中邻近所述漂移部分设置的绝缘部分和所述掺杂部分中的至少一个; 以及至少一个附加部分，其被设置为当在掺杂部分之间施加电压差时，显着地减小所述区域中的电场强度的变化。

    Synthesis process of dasatinib and intermediate thereof
    9.
    发明授权
    Synthesis process of dasatinib and intermediate thereof 有权
    达沙替尼及其中间体的合成方法

    公开(公告)号：US09108954B2

    公开(公告)日：2015-08-18

    申请号：US13576637

    申请日：2011-01-30

    申请人： Rong Yan ,  Hao Yang ,  Wen Hou ,  Yongxiang Xu

    发明人： Rong Yan ,  Hao Yang ,  Wen Hou ,  Yongxiang Xu

    IPC分类号： C07D417/12 ,  C07D417/14

    CPC分类号： C07D417/12

    摘要： Synthesis process of dasatinib is disclosed, which includes the step of reacting the compound of formula I with that of formula II to obtain the compound of formula III. Also disclosed is the compound of formula III which is used as an intermediate for synthesizing dasatinib. The substituents of R1, R2, R3 or R4 in formulae I, II or III are defined as in the description.

    摘要翻译： 公开了达沙替尼的合成方法，其包括使式I化合物与式II化合物反应以获得式III化合物的步骤。 还公开了用作合成达沙替尼的中间体的式III化合物。 式I，II或III中的R 1，R 2，R 3或R 4的取代基如描述中所定义。