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公开(公告)号:US20180012900A1
公开(公告)日:2018-01-11
申请号:US15541986
申请日:2015-01-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Wai Mun Wong , Leong Yap Chia , Ning Ge
IPC: G11C16/04
CPC classification number: H01L27/11521 , G11C16/0433 , H01L27/1156
Abstract: The present subject matter relates to an integrated circuit comprising an erasable programmable read only memory (EPROM) array having a plurality of EPROM cells disposed in rows and columns, wherein one or more EPROM cells located at predetermined positions in the EPROM array are selectively dischargeable. The one or more EPROM cells comprise a EPROM transistor having a first conductive layer to store electrons upon the EPROM transistor being programmed and a control metal oxide semiconductor field-effect transistor (MOSFET) electrically connected to the first conductive layer to provide an electron leakage path to dissipate the electrons stored in the first conductive layer in a predetermined leak time period.
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公开(公告)号:US20170243645A1
公开(公告)日:2017-08-24
申请号:US15521590
申请日:2014-11-25
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Leong Yap Chia , Ning Ge , Wai Mun Wong
CPC classification number: G11C13/0038 , B41J2/04541 , B41J2/04586 , B41J2/17546 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/15 , G11C2213/74 , G11C2213/79
Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.
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公开(公告)号:US20180134037A1
公开(公告)日:2018-05-17
申请号:US15558618
申请日:2015-07-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Wai Mun Wong , Leong Yap Chia , Ning Ge
CPC classification number: B41J2/05 , B41J2/14072 , B41J2/14129 , B41J2/16 , B41J2202/03 , B41J2202/11
Abstract: The present subject matter relates to a printhead assembly comprising a plurality of print nozzles in a nozzle array. Each of the plurality of print nozzles is coupled to a printhead firing resistor, the printhead firing resistor being individually addressable. A print control circuit is to actuate the printhead firing resistor. In accordance with one example implementation of the present subject matter, the print control circuit comprises pull-down resistors made of Tantalum-Aluminum (Ta—Al).
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公开(公告)号:US10173420B2
公开(公告)日:2019-01-08
申请号:US15558618
申请日:2015-07-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Wai Mun Wong , Leong Yap Chia , Ning Ge
Abstract: The present subject matter relates to a printhead assembly comprising a plurality of print nozzles in a nozzle array. Each of the plurality of print nozzles is coupled to a printhead firing resistor, the printhead firing resistor being individually addressable. A print control circuit is to actuate the printhead firing resistor. In accordance with one example implementation of the present subject matter, the print control circuit comprises pull-down resistors made of Tantalum-Aluminum (Ta—Al).
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公开(公告)号:US10081178B2
公开(公告)日:2018-09-25
申请号:US15877971
申请日:2018-01-23
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Ning Ge , Leong Yap Chia , Wai Mun Wong
CPC classification number: B41J2/04541 , B41J2/04543 , B41J2/0458 , B41J2/04581 , B41J2/04586 , G11C16/08 , G11C16/32
Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.
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公开(公告)号:US10224335B2
公开(公告)日:2019-03-05
申请号:US15541986
申请日:2015-01-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Wai Mun Wong , Leong Yap Chia , Ning Ge
IPC: H01L29/49 , H01L27/11521 , H01L27/1156 , G11C16/04
Abstract: The present subject matter relates to an integrated circuit comprising an erasable programmable read only memory (EPROM) array having a plurality of EPROM cells disposed in rows and columns, wherein one or more EPROM cells located at predetermined positions in the EPROM array are selectively dischargeable. The one or more EPROM cells comprise a EPROM transistor having a first conductive layer to store electrons upon the EPROM transistor being programmed and a control metal oxide semiconductor field-effect transistor (MOSFET) electrically connected to the first conductive layer to provide an electron leakage path to dissipate the electrons stored in the first conductive layer in a predetermined leak time period.
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公开(公告)号:US20180012654A1
公开(公告)日:2018-01-11
申请号:US15547123
申请日:2015-04-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Ning GE , Wai Mun Wong , Leong Yap Chia , Ser Chia Koh
CPC classification number: G11C13/0016 , B41J2/04541 , B41J2/0458 , B41J2/1753 , B41J2202/13 , G11C7/04 , G11C11/5664 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/146
Abstract: A memory cell includes an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor, and at least one address switch coupled to an address line to select the memory cell. A memory includes the bi-polar memristor and a one-way current conducting device, wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input.
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公开(公告)号:US20180009224A1
公开(公告)日:2018-01-11
申请号:US15547133
申请日:2015-04-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Ning GE , Zhiyong Li , Leong Yap Chia , Wai Mun Wong
IPC: B41J2/14 , G01N27/414
CPC classification number: B41J2/14153 , B41J2/125 , G01N27/414
Abstract: In an example, a device for sensing a property of a fluid may include an ion-sensitive field effect transistor (ISFET) having a gate, a source, and a drain. The device may also include a first metal element in contact with the gate and a switching layer in contact with the first metal layer. A resistance state of the switching layer is to be modified through application of an electrical field of at least a predefined strength through the switching layer and is to be retained in the switching layer following removal of the electrical field. The device may also include a metal plate in contact with the switching layer, in which the metal plate is to directly contact the fluid for which the property is to be sensed.
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公开(公告)号:US10170180B2
公开(公告)日:2019-01-01
申请号:US15547123
申请日:2015-04-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Ning Ge , Wai Mun Wong , Leong Yap Chia , Ser Chia Koh
Abstract: A memory cell includes an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor, and at least one address switch coupled to an address line to select the memory cell. A memory includes the bi-polar memristor and a one-way current conducting device, wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input.
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公开(公告)号:US10071552B2
公开(公告)日:2018-09-11
申请号:US15547133
申请日:2015-04-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Ning Ge , Zhiyong Li , Leong Yap Chia , Wai Mun Wong
IPC: B41J2/14 , G01N27/414
CPC classification number: B41J2/14153 , B41J2/125 , G01N27/414
Abstract: In an example, a device for sensing a property of a fluid may include an ion-sensitive field effect transistor (ISFET) having a gate, a source, and a drain. The device may also include a first metal element in contact with the gate and a switching layer in contact with the first metal layer. A resistance state of the switching layer is to be modified through application of an electrical field of at least a predefined strength through the switching layer and is to be retained in the switching layer following removal of the electrical field. The device may also include a metal plate in contact with the switching layer, in which the metal plate is to directly contact the fluid for which the property is to be sensed.
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