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公开(公告)号：US20230136006A1
公开(公告)日：2023-05-04
申请号：US18147852
申请日：2022-12-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
IPC: H04L49/00
Abstract: A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.
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2.发明申请METHOD, APPARATUS, AND COMMUNICATION NODE FOR SUPPRESSING OUTPUT NOISE OF PCIE DEVICES IN OPTICAL FIBER COMMUNICATION 有权用于抑制光纤通信中PCIE设备的输出噪声的方法，装置和通信节点公开(公告)号：US20160087723A1
公开(公告)日：2016-03-24
申请号：US14957621
申请日：2015-12-03
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor： Zhong ZHANG , Sheng LI , Yu HU , Xiaoyu GE , Yongyao LI , Xin QIU
IPC: H04B10/2507 , G06F13/42
CPC classification number: H04B10/2507 , G06F13/4282 , H04B10/0799 , H04B10/50 , H04B10/801
Abstract: A method, an apparatus, and a communication node for suppressing output noises of peripheral component interconnect express (PCIe) devices in optical fiber communication is provided. The communication node includes a PCIe chip and a detection and control circuit connected to a transmitting end of the PCIe chip. The PCIe chip transmits an electrical signal by a transmitter of a first lane. The detection and control circuit detects a differential-mode voltage of the electrical signal. If the differential-mode voltage is lower than a first threshold, the detection and control circuit controls an optical module connected to the PCIe chip not to transmit an optical signal through the first lane of the optical module. When a PCIe system includes the communication node, output noises of the transmitter is suppressed, and a normal optical fiber communication link is ensured.
Abstract translation: 提供了一种用于抑制光纤通信中的外围组件互连快速（PCIe）设备的输出噪声的方法，装置和通信节点。 通信节点包括PCIe芯片和连接到PCIe芯片的发送端的检测和控制电路。 PCIe芯片由第一通道的发射器发送电信号。 检测和控制电路检测电信号的差模电压。 如果差分模式电压低于第一阈值，则检测和控制电路控制连接到PCIe芯片的光模块不会通过光模块的第一通道发送光信号。 当PCIe系统包括通信节点时，发射机的输出噪声被抑制，并且确保了普通的光纤通信链路。
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公开(公告)号：US20240414032A1
公开(公告)日：2024-12-12
申请号：US18810900
申请日：2024-08-21
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yongyao LI , Fei LUO , Jiang ZHU
IPC: H04L25/03
Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. Accordingly, an equalization timeout period used for equalization training can be configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to ensure that an equalization parameter is found within the configured equalization timeout period, improving an equalization training success rate.
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公开(公告)号：US20230244617A1
公开(公告)日：2023-08-03
申请号：US18192019
申请日：2023-03-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Nianbing LI , Yongyao LI , Zhongjian CHEN , Shibin XU , Liangyi ZHANG
IPC: G06F13/16
CPC classification number: G06F13/1689
Abstract: This application provides a memory training method, a memory controller, a processor, and an electronic device. The memory controller keeps transmission delays of N DQs unchanged, adjusts a transmission delay of a DQS, and determines a maximum DQS transmission delay and/or a minimum DQS transmission delay of the DQS when all data carried in the N DQs is correctly transmitted. The memory controller adjusts the transmission delay of the DQS to a target DQS transmission delay between the maximum DQS transmission delay and the minimum DQS transmission delay. The method helps quickly align relative timing positions between the DQS and the N DQs. Therefore, memory training may be repeatedly performed in a working process of the processor, so that the N DQs keep enough timing margins.
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公开(公告)号：US20230094563A1
公开(公告)日：2023-03-30
申请号：US17959490
申请日：2022-10-04
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yongyao LI , Fei LUO , Er NIE
Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.
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Patent Agency Ranking
公开(公告)号：US20220200826A1
公开(公告)日：2022-06-23
申请号：US17557260
申请日：2021-12-21
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Junwei ZHONG , Yongyao LI
Abstract: A communication method is applicable to a processing apparatus that includes a processor and a communications interface. The processor determines a first parameter corresponding to the communications interface, wherein the communications interface is connected to at least one storage apparatus and communicates with the at least one storage apparatus based on the first parameter. In this way, the processor determines a parameter used to improve a quality of signal transmission and integrity during communication between the processing apparatus and the at least one storage apparatus.
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公开(公告)号：US20210263879A1
公开(公告)日：2021-08-26
申请号：US17315715
申请日：2021-05-10
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yongyao LI , Fei LUO , Jiankang LI , Jie WAN , Gongxian JIA
Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.
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公开(公告)号：US20240323148A1
公开(公告)日：2024-09-26
申请号：US18733318
申请日：2024-06-04
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
IPC: H04L49/00
CPC classification number: H04L49/3036
Abstract: A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.
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公开(公告)号：US20230402121A1
公开(公告)日：2023-12-14
申请号：US18455031
申请日：2023-08-24
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jun YU , Guoyu WANG , You LI , Yongyao LI
CPC classification number: G11C29/1201 , G11C29/12015 , G11C29/46
Abstract: Embodiments of the present disclosure provide a method for optimizing a flash memory chip and a related apparatus. The method comprises, after completing write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point that triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the trigger condition is related to working environmental data of the NFI; upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes a margin test; and upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI. In this way, the NFI bus channels can be optimized without disk disconnection.
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公开(公告)号：US20230091617A1
公开(公告)日：2023-03-23
申请号：US18070986
申请日：2022-11-29
Applicant: HUAWEI TECHNOLOGIES CO, LTD.
Inventor： Yongyao LI , Fei LUO , Jiang ZHU
IPC: H04L25/03
Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. According to this method, an equalization timeout period used for equalization training can be flexibly configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to better ensure that an equalization parameter is found within the configured equalization timeout period, thereby improving an equalization training success rate.
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