公开(公告)号：US07157329B2

公开(公告)日：2007-01-02

申请号：US11053508

申请日：2005-02-08

申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

IPC分类号： H01L21/8234

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 沟槽电容器的由表圈和存储板的顶表面形成的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

公开(公告)号：US20050158961A1

公开(公告)日：2005-07-21

申请号：US11053508

申请日：2005-02-08

申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 沟槽电容器的由表圈和存储板的顶表面形成的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

公开(公告)号：US06853025B2

公开(公告)日：2005-02-08

申请号：US10248801

申请日：2003-02-20

申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 由套环和储存板的顶表面形成的沟槽电容器的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

公开(公告)号：US20060024930A1

公开(公告)日：2006-02-02

申请号：US11235330

申请日：2005-09-26

申请人： Helmut Tews ,  Jochen Beintner

发明人： Helmut Tews ,  Jochen Beintner

IPC分类号： H01L21/425

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.

摘要翻译： 半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。 第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。 以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。 以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

公开(公告)号：US20060172486A1

公开(公告)日：2006-08-03

申请号：US11047312

申请日：2005-01-31

申请人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

发明人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L21/30604 ,  H01L29/66181

摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

公开(公告)号：US06599798B2

公开(公告)日：2003-07-29

申请号：US09910771

申请日：2001-07-24

申请人： Helmut Tews ,  Stephan Kudelka ,  Uwe Schroeder ,  Rolf Weis

发明人： Helmut Tews ,  Stephan Kudelka ,  Uwe Schroeder ,  Rolf Weis

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/76205 ,  H01L21/76235 ,  H01L27/10867 ,  H01L29/945

摘要： The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.

摘要翻译： 垂直DRAM电容器具有埋置的LOCOS环，其特征在于：自对准瓶和气相掺杂; 掩埋带深度不消耗硅; 没有减小沟槽直径; 以及在气相掺杂期间保护沟槽侧壁的氮化物层。

公开(公告)号：US06498061B2

公开(公告)日：2002-12-24

申请号：US09730674

申请日：2000-12-06

申请人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

发明人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

摘要翻译： 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

公开(公告)号：US06573137B1

公开(公告)日：2003-06-03

申请号：US09603442

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Wolfgang Bergner ,  Gary B. Bronner ,  Ulrike Gruening ,  Stephan Kudelka ,  Alexander Michaelis ,  Larry Nesbit ,  Carl J. Radens ,  Till Schloesser ,  Helmut Tews

发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Wolfgang Bergner ,  Gary B. Bronner ,  Ulrike Gruening ,  Stephan Kudelka ,  Alexander Michaelis ,  Larry Nesbit ,  Carl J. Radens ,  Till Schloesser ,  Helmut Tews

IPC分类号： H01L218242

CPC分类号： H01L27/10864

摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

摘要翻译： 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。 屏蔽材料沉积在存储电容器的节点导体上方。 一层硅沉积在阻挡材料上。 掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：US06740595B2

公开(公告)日：2004-05-25

申请号：US10122996

申请日：2002-04-12

申请人： Stephan Kudelka ,  Helmut Tews ,  Alexander Michaelis ,  Uwe Schroeder ,  Martin Popp ,  Kristin Schupke ,  Daniel Koehler

发明人： Stephan Kudelka ,  Helmut Tews ,  Alexander Michaelis ,  Uwe Schroeder ,  Martin Popp ,  Kristin Schupke ,  Daniel Koehler

IPC分类号： H01L21311

CPC分类号： H01L27/1087 ,  H01L21/30604 ,  H01L27/10829 ,  H01L29/66181

摘要： A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

摘要翻译： 一种通过将NH 4 OH溶液施加到多晶硅中来捕获半导体器件的多晶硅区域中的凹陷的方法。

公开(公告)号：US06437401B1

公开(公告)日：2002-08-20

申请号：US09824957

申请日：2001-04-03

申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

IPC分类号： H01L2976

CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。