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    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell
    4.
    发明申请
    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
    用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元

    公开(公告)号：US20050026384A1

    公开(公告)日：2005-02-03

    申请号：US10901406

    申请日：2004-07-27

    申请人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    发明人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

    摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

    摘要翻译： 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell
    5.
    发明授权
    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
    用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元

    公开(公告)号：US07273790B2

    公开(公告)日：2007-09-25

    申请号：US10901406

    申请日：2004-07-27

    申请人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sänger

    发明人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sänger

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

    摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

    摘要翻译： 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

    SENSOR APPARATUS, PRODUCTION METHOD AND DETECTION APPARATUS
    6.
    发明申请
    SENSOR APPARATUS, PRODUCTION METHOD AND DETECTION APPARATUS 有权
    传感器装置，生产方法和检测装置

    公开(公告)号：US20130187031A1

    公开(公告)日：2013-07-25

    申请号：US13355814

    申请日：2012-01-23

    申请人： Martin Popp ,  Beat De Coi

    发明人： Martin Popp ,  Beat De Coi

    IPC分类号： H01J40/14 ,  H01L31/18 ,  B82Y20/00

    CPC分类号： G01S17/36 ,  G01S7/4863 ,  G01S17/89

    摘要： A sensor apparatus including at least one analog and one digital circuit component and an analog/digital converter for converting analog signals of the analog circuit component into digital signals for the digital circuit component, and vice versa, wherein the analog circuit component and the digital circuit components include at least one module for electronically implementing a function, and wherein one of the modules of the analog circuit component is embodied as a sensor device for detecting optical radiation and one of the modules of the digital circuit component is embodied as a signal processing device for processing digital signals. In order to enable improved integration into application-based sensor devices, the circuit components including the analog/digital converter are integrated as an integrated circuit in a chip and the chip is manufactured as a semiconductor structure using 1-poly technology.

    摘要翻译： 一种传感器装置，包括至少一个模拟和一个数字电路部件和用于将模拟电路部件的模拟信号转换为数字电路部件的数字信号的模/数转换器，反之亦然，其中模拟电路部件和数字电路 组件包括用于电子地实现功能的至少一个模块，并且其中模拟电路部件的模块之一被实现为用于检测光辐射的传感器装置，并且数字电路部件的模块之一被实现为信号处理装置 用于处理数字信号。 为了能够改进集成到基于应用的传感器装置中，包括模拟/数字转换器的电路部件作为集成电路集成在芯片中，并且该芯片被制造为使用1-聚技术的半导体结构。

    4 F2 MEMORY CELL ARRAY
    7.
    发明申请
    4 F2 MEMORY CELL ARRAY 有权

    公开(公告)号：US20100097835A1

    公开(公告)日：2010-04-22

    申请号：US12252826

    申请日：2008-10-16

    申请人： Martin Popp ,  Till Schloesser

    发明人： Martin Popp ,  Till Schloesser

    IPC分类号： G11C5/06 ,  G11C11/24

    CPC分类号： G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

    摘要： An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.

    摘要翻译： 包括存储单元阵列的集成电路包括有源区线，位线，所述位线被布置成使得单独的位线与多个有源区域线相交以分别形成位线接触，位线布置在位线间距处，字线 被布置为使得单个字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，字线以字线间距排列，其中相邻位线接触，每个 连接到有源区线之一，与不同的位线连接，位线间距与字线间距不同。

    MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES
    8.
    发明申请
    MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES 失效
    存储单元阵列包含闪烁的位线

    公开(公告)号：US20100096669A1

    公开(公告)日：2010-04-22

    申请号：US12252853

    申请日：2008-10-16

    申请人： Martin Popp ,  Till Schloesser

    发明人： Martin Popp ,  Till Schloesser

    IPC分类号： H01L29/76 ,  H01L27/108

    CPC分类号： H01L27/10885 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10891

    摘要： An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

    摘要翻译： 包括存储单元阵列的集成电路包括沿着并行有源区域线，位线布置的晶体管，位线被布置成使得各个相互交叉的多个有源区域线分别形成位线接触，位线形成为 摆动的线条，字线被布置成使得字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，其中相邻的位线接触，其中每一个连接到一个 的有源面积线与不同的位线连接。

    Transistor, memory cell, memory cell array and method of forming a memory cell array
    9.
    发明授权
    Transistor, memory cell, memory cell array and method of forming a memory cell array 失效
    晶体管，存储单元，存储单元阵列和形成存储单元阵列的方法

    公开(公告)号：US07700983B2

    公开(公告)日：2010-04-20

    申请号：US11300853

    申请日：2005-12-15

    申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

    摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

    摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。

    Integrated circuit having a memory cell array and method of forming an integrated circuit
    10.
    发明授权
    Integrated circuit having a memory cell array and method of forming an integrated circuit 失效
    具有存储单元阵列的集成电路和形成集成电路的方法

    公开(公告)号：US07642572B2

    公开(公告)日：2010-01-05

    申请号：US11735164

    申请日：2007-04-13

    申请人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

    发明人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

    摘要翻译： 公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。 一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。 位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。 相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。 以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。