公开(公告)号：US06944003B2

公开(公告)日：2005-09-13

申请号：US10365527

申请日：2003-02-13

申请人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

发明人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

IPC分类号： G01R31/28 ,  H01L21/66 ,  H02H9/04 ,  H02H3/24

CPC分类号： H02H9/046

摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

摘要翻译： 第一半导体集成电路通过电缆连接到第二半导体集成电路。 在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。 第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。 在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作 强制。 因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。 因此，在低电压条件下可以进行运行评估。

公开(公告)号：US06417700B1

公开(公告)日：2002-07-09

申请号：US09978676

申请日：2001-10-18

申请人： Takashi Hirata ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Yoshihide Komatsu ,  Yutaka Terada ,  Hirokazu Sugimoto

发明人： Takashi Hirata ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Yoshihide Komatsu ,  Yutaka Terada ,  Hirokazu Sugimoto

IPC分类号： H03K5153

CPC分类号： H03M1/0626 ,  H03M1/0872 ,  H03M1/145 ,  H03M1/34 ,  H03M1/36

摘要： In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

摘要翻译： 在用于检测模拟信号的电压电平的电路中，转换电路通过将模拟信号的电压电平与多个参考电位进行比较来将模拟信号转换成数字信号。 滤波器电路将数字信号的上升沿或下降沿的至少任一个彼此的定时相匹配。 这可以防止电压电平检测中的故障。

公开(公告)号：US06943595B2

公开(公告)日：2005-09-13

申请号：US10670510

申请日：2003-09-26

申请人： Hirokazu Sugimoto ,  Toru Iwata ,  Takashi Hirata

发明人： Hirokazu Sugimoto ,  Toru Iwata ,  Takashi Hirata

IPC分类号： H04L25/40 ,  H03K5/00 ,  H03K5/135 ,  H04L7/00 ,  H04L7/02 ,  H04L7/04 ,  H03L7/00

CPC分类号： H03K5/135 ,  H03K2005/00156 ,  H04L7/0008 ,  H04L7/02

摘要： A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

摘要翻译： 同步电路包括：状态检测电路，用于根据输入信号的转变点和同步时钟的边沿之间的时间关系输出控制信号;延迟选择电路，用于根据控制信号向输入信号添加延迟 信号和用于使从延迟选择电路输出的信号与同步时钟同步的锁存电路。 因此，可以在不增加输入信号的延迟的情况下执行输入信号的同步。

公开(公告)号：US20100245663A1

公开(公告)日：2010-09-30

申请号：US12376405

申请日：2007-07-31

申请人： Manabu Kawabata ,  Ryogo Yanagisawa ,  Toru Iwata ,  Hirokazu Sugimoto

发明人： Manabu Kawabata ,  Ryogo Yanagisawa ,  Toru Iwata ,  Hirokazu Sugimoto

IPC分类号： H04N7/01 ,  G06F1/04 ,  H04N5/05

CPC分类号： H03K5/135 ,  H03L7/18 ,  H03M9/00 ,  H04L7/0008

摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

摘要翻译： 一种用于接收并行数据信号和第一时钟信号并输出​​串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟 信号X / Y。 第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号 缩放器（16），与第四时钟信号同步地连接到串行数据信号。 分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟​​信号之一作为第二时钟信号。

公开(公告)号：US20110074465A1

公开(公告)日：2011-03-31

申请号：US12963998

申请日：2010-12-09

申请人： Tomoko CHIBA ,  Hirokazu Sugimoto ,  Toru Iwata

发明人： Tomoko CHIBA ,  Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H03K19/0175

CPC分类号： H04L25/028 ,  H03K19/003 ,  H03K19/017527

摘要： A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

摘要翻译： 驱动器通过供电节点提供数据信号。 电压松弛晶体管具有连接到驱动器的电源节点的源极，连接到连接到信号线的信号节点的漏极和施加信号节点处的电压的栅极。

公开(公告)号：US08004433B2

公开(公告)日：2011-08-23

申请号：US12376405

申请日：2007-07-31

申请人： Manabu Kawabata ,  Ryogo Yanagisawa ,  Toru Iwata ,  Hirokazu Sugimoto

发明人： Manabu Kawabata ,  Ryogo Yanagisawa ,  Toru Iwata ,  Hirokazu Sugimoto

IPC分类号： H03M9/00

CPC分类号： H03K5/135 ,  H03L7/18 ,  H03M9/00 ,  H04L7/0008

摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

摘要翻译： 一种用于接收并行数据信号和第一时钟信号并输出​​串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟 信号X / Y。 第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号 缩放器（16），与第四时钟信号同步地连接到串行数据信号。 分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟​​信号之一作为第二时钟信号。

公开(公告)号：US07957498B2

公开(公告)日：2011-06-07

申请号：US11995423

申请日：2006-07-10

申请人： Hirokazu Sugimoto ,  Toru Iwata

发明人： Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H04L7/00

CPC分类号： H04L7/0004 ,  H04L25/14

摘要： The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.

摘要翻译： 数据接收装置包括：位相位同步电路（10），用于执行接收数据信号的相位调整，以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路（10）的数据信号基于由位相位同步电路（10）相位调整的数据信号而处于稳定状态，则输出检测信号的状态检测电路（20） ）和相应的时钟信号。 位相位同步电路（10）在接收到检测信号时初始化数据信号的相位调整。

公开(公告)号：US20090086852A1

公开(公告)日：2009-04-02

申请号：US11995423

申请日：2006-07-10

申请人： Hirokazu Sugimoto ,  Toru Iwata

发明人： Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H04L7/06

CPC分类号： H04L7/0004 ,  H04L25/14

摘要： The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.

摘要翻译： 数据接收装置包括：位相位同步电路（10），用于执行接收数据信号的相位调整，以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路（10）的数据信号基于由位相位同步电路（10）相位调整的数据信号而处于稳定状态，则输出检测信号的状态检测电路（20） ）和相应的时钟信号。 位相位同步电路（10）在接收到检测信号时初始化数据信号的相位调整。

公开(公告)号：US08228093B2

公开(公告)日：2012-07-24

申请号：US12963998

申请日：2010-12-09

申请人： Tomoko Chiba ,  Hirokazu Sugimoto ,  Toru Iwata

发明人： Tomoko Chiba ,  Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H03K19/0175

CPC分类号： H04L25/028 ,  H03K19/003 ,  H03K19/017527

摘要： A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

摘要翻译： 驱动器通过供电节点提供数据信号。 电压松弛晶体管具有连接到驱动器的电源节点的源极，连接到连接到信号线的信号节点的漏极和施加信号节点处的电压的栅极。

公开(公告)号：US07809084B2

公开(公告)日：2010-10-05

申请号：US11597794

申请日：2005-02-01

申请人： Hirokazu Sugimoto ,  Toru Iwata

发明人： Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H03K9/00

CPC分类号： G11B20/10009 ,  G09G5/006 ,  G09G5/12 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/14 ,  G11B2020/10592 ,  G11B2220/2562 ,  H04N5/775 ,  H04N5/781

摘要： In a signal receiving circuit there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. The selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels.

摘要翻译： 在信号接收电路中，提供有N个输入检测电路2a至2n，用于接收信号S1至SN的N个信道中包括的时钟信号S1-c至SN-c。 每个输入检测电路2a至2n检测相应信道的输入信号的转变，并进一步确认在转换检测之后正在接收相应信道的信号，从而检测相应信道的信号的输入。 选择电路3选择并输出检测到输入的信道的信号中的时钟信号和数据信号。 所选择的输出信号通过由N个信道共享的相位同步电路4，串行/并行转换电路5等中的每一个依次进行输入处理。