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83 条记录 (耗时 0.036 秒)

    Power MISFET semiconductor device
    8.
    发明授权
    Power MISFET semiconductor device 有权
    功率MISFET半导体器件

    公开(公告)号：US08455943B2

    公开(公告)日：2013-06-04

    申请号：US13181816

    申请日：2011-07-13

    申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

    发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

    IPC分类号： H01L29/66 ,  H01L29/40

    CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806

    摘要： Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

    摘要翻译： 提供了一种在一个半导体衬底上具有功率MISFET和肖特基势垒二极管的半导体器件中的技术，其能够抑制功率MISFET的导通电阻的急剧增加，同时使肖特基势垒二极管的雪崩击穿电压更大 比功率MISFET。 在本发明中，在半导体衬底上形成两个外延层，一个具有高掺杂浓度且另一个具有低掺杂浓度的外延层，并且这两个外延层之间的边界位于相同深度或更浅的区域 沟槽的底部。

    Method of manufacturing a superjunction power MOSFET with self-aligned trench gate
    9.
    发明授权
    Method of manufacturing a superjunction power MOSFET with self-aligned trench gate 有权
    制造具有自对准沟槽栅极的超结功率MOSFET的方法

    公开(公告)号：US07595242B2

    公开(公告)日：2009-09-29

    申请号：US11958363

    申请日：2007-12-17

    申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

    发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

    摘要翻译： 提供高性能的沟槽栅型功率晶体管。 作为栅电极的沟槽栅极形成为包括漏极层和外延层的超结结构。 在这种情况下，栅电极形成为使得外延层的上表面高于在漏极层上形成的沟道层的上表面。 然后，在沟道层和外延层的每一个上形成绝缘膜，然后去除绝缘膜的一部分，以在外延层的侧壁上形成侧壁间隔物。 随后，以侧壁间隔物作为掩模，去除沟道层的一部分和漏极层的一部分，以形成用于沟槽栅的沟槽。

    IGBT and diode
    10.
    发明授权
    IGBT and diode 有权
    IGBT和二极管

    公开(公告)号：US09064839B2

    公开(公告)日：2015-06-23

    申请号：US13470412

    申请日：2012-05-14

    申请人： Hitoshi Matsuura ,  Makoto Koshimizu ,  Yoshito Nakazawa

    发明人： Hitoshi Matsuura ,  Makoto Koshimizu ,  Yoshito Nakazawa

    IPC分类号： H01L29/76 ,  H01L29/74 ,  H01L29/36 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

    CPC分类号： H01L29/66348 ,  H01L21/265 ,  H01L29/0615 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7397 ,  H01L29/8611

    摘要： In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N−-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N−-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N−-type drift region. The N−-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N−-type drift region.

    摘要翻译： 在IGBT中，通过离子注入产生的缺陷将导致P型集电极区域或N型缓冲区域导入N型缓冲区域附近的N型漂移区域中，从而提高开关速度，但是漏电流 通过使耗尽层在关闭时与晶体缺陷接触而增加。 为了避免这种情况，提供了一种IGBT，其包括具有比N型漂移区的浓度高的N型缓冲区，并且在其背面与P型接触，并且在靠近 N型缓冲区和N型漂移区之间的边界。 相对于缺陷剩余区域位于前表面侧的N型漂移区设置有具有比N型漂移区的浓度高的N型场停止区。