公开(公告)号：US3676231A

公开(公告)日：1972-07-11

申请号：US3676231D

申请日：1970-02-20

Applicant: IBM

Inventor： MEDVECKY BARTHOLOMEW P ,  OBERAI AVTAR S ,  PLATT ALAN

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/22 ,  H01L21/225 ,  H01L21/331 ,  H01L7/44

CPC classification number: H01L21/2252 ,  H01L21/00

Abstract: A METHOD FOR PRODUCING A DIFFUSED BORON REGION IN A SILICON SEMICONDUCTOR HAVING AN IMPURITY PROFILE CHARACTERIZED AS A STEP FUNCTION AND HAVING A SURFACE IMPURITY CONCENTRATION LESS THAN THE SOLID SOLUBILITY OF BORON IN SILICON WHEREIN THE BODY IS EXPOSED TO A GASEOUS MIXTURE OF O2, AND BBR3, AND AN INERT CARRIER GAS AT AN ELEVATED TEMPERATURE WHICH FORMS A GLASSY BORON RICH LAYER, AND SUBSEQUENTLY HEATING THE RESULTANT BODY IN AN OXIDIZING ENVIROMENT, OR A COMBINATION OXIDIZING AND NONOXIDIZING ENVIROMENTS, TO INCREASE THE DEPTH OF THE DIFFUSED REGION AND SIMULTANEOUSLY REDUCE THE SURFACE CONCENTRATION PRODUCING A PROFILE HAVING A STEP FUNCTION CONFIGURATION.

公开(公告)号：US3672983A

公开(公告)日：1972-06-27

申请号：US3672983D

申请日：1970-01-09

Applicant: IBM

Inventor： WITT DAVID DE ,  DHAKA VIR A ,  OBERAI AVTAR S

IPC: H01L23/522 ,  H01L21/283 ,  H01L21/329 ,  H01L21/331 ,  H01L21/768 ,  H01L23/29 ,  H01L23/485 ,  H01L29/73 ,  H01L7/34

CPC classification number: H01L23/29 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/173 ,  H01L2924/00

Abstract: IN A SEMICONDUCTOR DEVICE, THE EMITTER AND BASE METAL CONTACT STRIPES ARE AT DIFFERENT LEVELS AND ARE SEPARATED BY SILICON DIOXIDE AND SILICON NITRIDE. BY USING SUCH A SILICON DIOXIDE SEPARATORY LAYER IN COMBINATION WITH AN INITIAL SILICON NITRIDE COATING OVER THE EMITTER AND BASE REGIONS IN THE SEMICONDUCTOR SUBSTRATE, THE SILICON NITRIDE COATING BEING ETCHED DURING PROCESSING, A HIGH SPEED TRANSISTOR HAVING A VERY SMALL EMITTER-BASE CONTACT SPACING, AND A SMALL EMITTER STRIPE WIDTH IS OBTAINED.

D R A W I N G

公开(公告)号：US3622842A

公开(公告)日：1971-11-23

申请号：US3622842D

申请日：1969-12-29

Applicant: IBM

Inventor： OBERAI AVTAR S

IPC: H01L21/00 ,  H01L21/761 ,  H01L23/485 ,  H01L29/08 ,  H01L19/00

CPC classification number: H01L29/0821 ,  H01L21/00 ,  H01L21/761 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S257/918 ,  H01L2924/00

Abstract: A transistor of a monolithic integrated circuit has its switching speed increased by reducing the parasitic collector capacitance through reducing the junction area between the base and the subcollector. By controlling the thickness and impurity concentration of a layer into which the subcollector region is diffused to prevent punch through of the base to the substrate of the same conductivity as the base or a layer, which is on the substrate, of the same conductivity as the base and beneath the controlled layer, the subcollector region need be positioned only beneath the emitter region and not the entire area of the base region.