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    Field effect transistor capacitor storage cell
    3.
    发明授权
    Field effect transistor capacitor storage cell 失效
    场效应晶体管电容器存储单元

    公开(公告)号：US3585613A

    公开(公告)日：1971-06-15

    申请号：US3585613D

    申请日：1969-08-27

    Applicant: IBM

    Inventor： PALFI THOMAS L

    IPC: G11C11/41 ,  G11C11/24 ,  G11C11/405 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40 ,  G11C5/02 ,  G11C7/00

    CPC classification number: H01L27/108 ,  G11C11/405

    Abstract: A nondestructive read integrated circuit memory having a twodimensional array of insulated-gate field-effect transistor cells. Each cell consists of three transistors, an input isolation transistor, an output isolation transistor and a storage transistor. The cells in the array are interconnected along one dimension by bit sense lines and along a second dimension by Phi 1 and Phi 2 control lines. Only the cells which are selected by the control lines are operative during a read or write cycle, and the remaining cells are isolated from the active cells by means of the unactivated input and output isolation transistors. The input isolation transistor, when activated during a write cycle controls the placement of a charge which represents storage information across the gate to substrate capacitance of the storage transistor. The output isolation transistor, when activated during a read cycle controls the sensing of information stored at the storage transistor.

    Method of making a common emitter transistor integrated circuit structure
    4.
    发明授权
    Method of making a common emitter transistor integrated circuit structure 失效
    制造公共发射极晶体管集成电路结构的方法

    公开(公告)号：US3865648A

    公开(公告)日：1975-02-11

    申请号：US42575473

    申请日：1973-12-10

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G ,  NORTH WILLIAM D ,  PALFI THOMAS L

    IPC: H01L21/761 ,  H01L27/00 ,  H01L7/36 ,  B01J17/00 ,  H01L29/72

    CPC classification number: H01L21/761 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151

    Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

    Abstract translation: 一种平面集成半导体电路，具有通过与其中形成集成电路的半导体部件的主体形成PN或整流的发射极区彼此隔离并与其它晶体管隔离的共同发射极晶体管元件。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

    Common emitter transistor integrated circuit structure
    5.
    发明授权
    Common emitter transistor integrated circuit structure 失效
    共同发光二极管集成电路结构

    公开(公告)号：US3648130A

    公开(公告)日：1972-03-07

    申请号：US3648130D

    申请日：1969-07-16

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G ,  NORTH WILLIAM D ,  PALFI THOMAS L

    IPC: F16N27/00 ,  H01L23/535 ,  H01L27/00 ,  H01L27/102 ,  H01L29/417 ,  H01L19/00

    CPC classification number: H01L29/41708 ,  F16N27/00 ,  H01L23/535 ,  H01L27/00 ,  H01L27/1025 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151 ,  H01L2924/00

    Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN- or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

    Abstract translation: 一种平面集成半导体电路，其具有通过发射极区彼此隔离并且与其它晶体管隔离的共同发射极晶体管元件，其与形成集成电路的半导体元件的主体形成PN或整流结。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

    Integrated memory cell circuit
    6.
    发明授权
    Integrated memory cell circuit 失效
    集成存储单元电路

    公开(公告)号：US3610967A

    公开(公告)日：1971-10-05

    申请号：US3610967D

    申请日：1970-02-27

    Applicant: IBM

    Inventor： PALFI THOMAS L

    IPC: G11C11/412 ,  H01L27/07 ,  H01L19/00

    CPC classification number: G11C11/412 ,  H01L27/0727

    Abstract: Method and means for constructing memory cell circuits, comprising the addition of a single diffusion to an IGFET wafer to form diodes in the drain or source regions of at least one of the FETS in the wafer, thus reducing the number of FETS in the cell and substantially reducing the area occupied by each cell. Three embodiments are disclosed, all using diodes as the input/output components of the cells and, in addition, one uses two diodes as the load, giving an exponential load characteristic, while another combines a diode and FET in the load to give a semiexponential load characteristic.

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