公开(公告)号：US3301213A

公开(公告)日：1967-01-31

申请号：US23245662

申请日：1962-10-23

Applicant: IBM

Inventor： GROCHOWSKI EDWARD G ,  SCHWARTZ ROBERT S ,  WHITE WILLIAM H

IPC: C23C16/00 ,  C30B25/08 ,  C30B35/00 ,  H01L21/20

CPC classification number: C30B35/00 ,  C23C16/00 ,  C30B25/08

公开(公告)号：US3602192A

公开(公告)日：1971-08-31

申请号：US3602192D

申请日：1969-05-19

Applicant: IBM

Inventor： GROCHOWSKI EDWARD G ,  LYONS VINCENT J

IPC: C30B25/02 ,  B01J19/00 ,  B01J19/28 ,  C23C16/54 ,  H01L21/205 ,  H01L21/22 ,  H01L21/302 ,  H01L21/31 ,  H01L21/677 ,  C23C11/00

CPC classification number: C23C16/54

Abstract: The continuous processing of semiconductor wafers transported through a reactor system having a series of reaction zones permitting separate process functions, with zone isolation achieved through the use of dynamically sealed vapor-purged isolation chambers. An in-line, verticaL arrangement of gas inlets and outlets and planar work supports effect a laminar flow of gaseous materials.

公开(公告)号：US3523046A

公开(公告)日：1970-08-04

申请号：US3523046D

申请日：1964-09-14

Applicant: IBM

Inventor： GROCHOWSKI EDWARD G ,  LYONS VINCENT J

IPC: C30B25/02 ,  H01L21/00 ,  H01L7/36

CPC classification number: C30B29/06 ,  C30B25/02 ,  H01L21/00 ,  Y10S148/007 ,  Y10S438/925

公开(公告)号：US3865648A

公开(公告)日：1975-02-11

申请号：US42575473

申请日：1973-12-10

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G ,  NORTH WILLIAM D ,  PALFI THOMAS L

IPC: H01L21/761 ,  H01L27/00 ,  H01L7/36 ,  B01J17/00 ,  H01L29/72

CPC classification number: H01L21/761 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151

Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

Abstract translation: 一种平面集成半导体电路，具有通过与其中形成集成电路的半导体部件的主体形成PN或整流的发射极区彼此隔离并与其它晶体管隔离的共同发射极晶体管元件。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

公开(公告)号：US3648130A

公开(公告)日：1972-03-07

申请号：US3648130D

申请日：1969-07-16

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G ,  NORTH WILLIAM D ,  PALFI THOMAS L

IPC: F16N27/00 ,  H01L23/535 ,  H01L27/00 ,  H01L27/102 ,  H01L29/417 ,  H01L19/00

CPC classification number: H01L29/41708 ,  F16N27/00 ,  H01L23/535 ,  H01L27/00 ,  H01L27/1025 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151 ,  H01L2924/00

Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN- or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

Abstract translation: 一种平面集成半导体电路，其具有通过发射极区彼此隔离并且与其它晶体管隔离的共同发射极晶体管元件，其与形成集成电路的半导体元件的主体形成PN或整流结。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

公开(公告)号：US3585464A

公开(公告)日：1971-06-15

申请号：US3585464D

申请日：1967-10-19

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  HESS MARTIN S ,  MAHERAS GEORGE ,  NORTH WILLIAM D ,  GROCHOWSKI EDWARD G

IPC: H01L21/822 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/04 ,  H01L29/04 ,  H01L29/73 ,  H01L19/00

CPC classification number: H01L29/045 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S438/91 ,  Y10S438/973

Abstract: A semiconductor device and a method for fabricating the same which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a plane with a plurality of semiconductor devices within the substrate is described. The devices are isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less than approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.

公开(公告)号：US3573974A

公开(公告)日：1971-04-06

申请号：US3573974D

申请日：1968-03-21

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G

IPC: C23C16/12 ,  H01L21/00 ,  H01L23/485 ,  C23C11/02 ,  H01L7/00

CPC classification number: H01L21/00 ,  C23C16/12 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/913 ,  H01L2924/00

Abstract: A METHOD FOR FORMING ALUMINUM OHMIC CONTACTS AND CONDUCTIVE CONNECTORS ON SEMICONDUCTOR DEVICES HAVING SILICON DIOXIDE PASSIVATING MASKS COVERING PORTIONS OF A SEMICONDUCTOR SUBSTRATE. THE ALUMINUM CONTACTS AND CONNECTORS ARE FORMED BY THE DISPROPORTIONATION OF ALUMINUM MONO-HALIDE VAPOR IN THE PRESENCE OF THE SILICON DIOXIDE

MASKED SUBSTRATE. THE ALUMINUM FORMED BY THE DISPROPORTIONATION IS DEPOSITED AS A LAYER OVER THE MASKED SUBSTRATE. THEN, PORTIONS OF THE ALUMINUM LAYER ARE SELECTIVELY REMOVED TO LEAVE A PATTERN OHMIC CONTACTS AND CONDUCTIVE CONNECTORS.