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公开(公告)号:US12204996B2
公开(公告)日:2025-01-21
申请号:US17645209
申请日:2021-12-20
Applicant: IMEC vzw
Inventor: Fahd Ayyalil Mohiyaddin , Ruoyu Li , Bogdan Govoreanu , Steven Brebels
IPC: G06N10/40
Abstract: An integrated system for quantum computation is provided, In one aspect, the system includes at least one semiconductor spin quantum bit (qubit); a feedline configured to act as an electron spin resonance (ESR) antenna for control of the at least one qubit; at least one resonator; and a ground plane common to both the feedline and the at least one resonator. The at least one resonator is capacitively coupled to the feedline, and configured for readout of the at least one qubit via the feedline. The feedline and the at least one resonator are arranged in adjacent layers separated by at least a dielectric. A corresponding method of performing quantum computation using such an integrated system is also provided.
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公开(公告)号:US20230196166A1
公开(公告)日:2023-06-22
申请号:US18060154
申请日:2022-11-30
Applicant: IMEC VZW
Inventor: Fahd Ayyalil Mohiyaddin , Stefan Kubicek , Clement Godfrin , Bogdan Govoreanu , Steven Brebels , Ruoyu Li , George Eduard Simion
Abstract: A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.
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公开(公告)号:US11638391B2
公开(公告)日:2023-04-25
申请号:US17345827
申请日:2021-06-11
Applicant: IMEC VZW
Inventor: Boon Teik Chan , Ruoyu Li , Stefan Kubicek , Julien Jussot
Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.
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公开(公告)号:US12027610B2
公开(公告)日:2024-07-02
申请号:US17474175
申请日:2021-09-14
Applicant: IMEC VZW
Inventor: George Eduard Simion , Fahd Ayyalil Mohiyaddin , Stefan Kubicek , Bogdan Govoreanu , Florin Ciubotaru , Ruoyu Li
CPC classification number: H01L29/66977 , G06N10/00 , H10N50/80 , B82Y10/00
Abstract: According to an aspect of the present inventive concept there is provided a qubit device comprising: a semiconductor substrate layer; a set of control gates configured to define a row of electrostatically confined quantum dots along the substrate layer, each quantum dot being suitable for holding a qubit; and a set of nanomagnets arranged in a row over the substrate layer such that a nanomagnet is arranged above every other quantum dot of the row of quantum dots, wherein each nanomagnet has an out-of-plane magnetization with respect to the substrate layer and wherein every other quantum dot is subjected to an out-of-plane magnetic field generated by a respective nanomagnet, such that a qubit spin resonance frequency of every other quantum dot is shifted with respect to an adjacent quantum dot of the row of quantum dots.
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公开(公告)号:US20210391526A1
公开(公告)日:2021-12-16
申请号:US17345827
申请日:2021-06-11
Applicant: IMEC VZW
Inventor: Boon Teik Chan , Ruoyu Li , Stefan Kubicek , Julien Jussot
Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.
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