公开(公告)号：US12027610B2

公开(公告)日：2024-07-02

申请号：US17474175

申请日：2021-09-14

Applicant: IMEC VZW

Inventor： George Eduard Simion ,  Fahd Ayyalil Mohiyaddin ,  Stefan Kubicek ,  Bogdan Govoreanu ,  Florin Ciubotaru ,  Ruoyu Li

IPC: H01L29/66 ,  G06N10/00 ,  H10N50/80 ,  B82Y10/00

CPC classification number: H01L29/66977 ,  G06N10/00 ,  H10N50/80 ,  B82Y10/00

Abstract: According to an aspect of the present inventive concept there is provided a qubit device comprising: a semiconductor substrate layer; a set of control gates configured to define a row of electrostatically confined quantum dots along the substrate layer, each quantum dot being suitable for holding a qubit; and a set of nanomagnets arranged in a row over the substrate layer such that a nanomagnet is arranged above every other quantum dot of the row of quantum dots, wherein each nanomagnet has an out-of-plane magnetization with respect to the substrate layer and wherein every other quantum dot is subjected to an out-of-plane magnetic field generated by a respective nanomagnet, such that a qubit spin resonance frequency of every other quantum dot is shifted with respect to an adjacent quantum dot of the row of quantum dots.

公开(公告)号：US12204996B2

公开(公告)日：2025-01-21

申请号：US17645209

申请日：2021-12-20

Applicant: IMEC vzw

Inventor： Fahd Ayyalil Mohiyaddin ,  Ruoyu Li ,  Bogdan Govoreanu ,  Steven Brebels

IPC: G06N10/40

Abstract: An integrated system for quantum computation is provided, In one aspect, the system includes at least one semiconductor spin quantum bit (qubit); a feedline configured to act as an electron spin resonance (ESR) antenna for control of the at least one qubit; at least one resonator; and a ground plane common to both the feedline and the at least one resonator. The at least one resonator is capacitively coupled to the feedline, and configured for readout of the at least one qubit via the feedline. The feedline and the at least one resonator are arranged in adjacent layers separated by at least a dielectric. A corresponding method of performing quantum computation using such an integrated system is also provided.

公开(公告)号：US20170358742A1

公开(公告)日：2017-12-14

申请号：US15625941

申请日：2017-06-16

Applicant: IMEC VZW

Inventor： Bogdan Govoreanu

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1641

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to memory or storage devices based on resistive switching, and to methods of making and using such devices. In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. The first inner region includes one or more metal oxide layers and the second inner region consists of a plurality of layers, where each of the layers of the second inner region is an insulating, a semi-insulating or a semiconducting layer. The second inner region comprises one or more layers having a stoichiometric or off-stoichiometric composition of a material selected from the group consisting of SiGex, SiNx, AlOx, MgOx, AlNx, SiNx, HfOx, HfSiOx, ZrOx, ZrSiOx, GdAlOx, DyScOx, TaOx and combinations thereof. The second inner region comprises one or more silicon-containing layers, such that one of the one or more silicon-containing layers contacts the first inner region.

公开(公告)号：US20230200263A1

公开(公告)日：2023-06-22

申请号：US18060389

申请日：2022-11-30

Applicant: IMEC VZW

Inventor： Jaber Derakhshandeh ,  Iuliana Radu ,  Eric Beyne ,  Bogdan Govoreanu

IPC: H10N69/00 ,  H01L23/00 ,  H01L23/538

CPC classification number: H10N69/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/05 ,  H01L24/08 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/06 ,  H01L2224/13109 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/05609 ,  H01L2224/08225 ,  H01L2224/0557 ,  H01L2224/06181

Abstract: The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

公开(公告)号：US20230196166A1

公开(公告)日：2023-06-22

申请号：US18060154

申请日：2022-11-30

Applicant: IMEC VZW

Inventor： Fahd Ayyalil Mohiyaddin ,  Stefan Kubicek ,  Clement Godfrin ,  Bogdan Govoreanu ,  Steven Brebels ,  Ruoyu Li ,  George Eduard Simion

IPC: G06N10/40 ,  G06N10/20 ,  H10N69/00

CPC classification number: G06N10/40 ,  G06N10/20 ,  H10N69/00

Abstract: A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.

公开(公告)号：US09786795B2

公开(公告)日：2017-10-10

申请号：US14508906

申请日：2014-10-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Bogdan Govoreanu ,  Christoph Adelmann ,  Leqi Zhang ,  Malgorzata Jurczak

IPC: H01L29/861 ,  H01L29/16 ,  H01L29/45 ,  H01L45/00 ,  H01L29/88 ,  H01L27/24

CPC classification number: H01L29/861 ,  H01L27/2418 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/456 ,  H01L29/88 ,  H01L45/00

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.

公开(公告)号：US09595668B2

公开(公告)日：2017-03-14

申请号：US14306116

申请日：2014-06-16

Applicant: IMEC vzw

Inventor： Bogdan Govoreanu

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/12 ,  G11C13/0002 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (ki), a conduction band offset (Φi), and a thickness, wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及具有电阻开关元件的存储器件以及操作这种存储器件的方法。 一方面，存储单元包括由金属材料或半导体材料之一形成的第一电极和第二电极。 存储单元还包括形成在第一电极和第二电极之间的电阻切换元件。 存储单元还包括形成在电阻切换元件和第一电极之间的隧道整流器。 隧道整流器包括多层隧道堆叠，其包括至少两个各自具有介电常数（ki），导带偏移（Φi）和厚度的电介质层，其中介电层之一具有较高的介电常数， 与多层隧道堆叠的任何其它介电层相比较低的导带偏移和更高的厚度。