公开(公告)号：US20240079051A1

公开(公告)日：2024-03-07

申请号：US17983331

申请日：2022-11-08

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Tuo-Hung Hou ,  Fu-Cheng Tsai ,  Jian-Wei Su ,  Kuo-Hua Tseng

IPC: G11C11/412 ,  G11C11/418

CPC classification number: G11C11/412 ,  G11C11/418

Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

公开(公告)号：US12265904B2

公开(公告)日：2025-04-01

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/045 ,  G06N3/0455

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US11145356B2

公开(公告)日：2021-10-12

申请号：US16850016

申请日：2020-04-16

Applicant: Industrial Technology Research Institute

Inventor： Fu-Cheng Tsai ,  Heng-Yuan Lee ,  Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou

IPC: G11C11/34 ,  G11C11/408 ,  G11C11/56 ,  G11C11/4099 ,  G11C11/4091

Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.

公开(公告)号：US20210004678A1

公开(公告)日：2021-01-07

申请号：US16846427

申请日：2020-04-13

Applicant: Industrial Technology Research Institute

Inventor： Shih-Chieh Chang ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Heng-Yuan Lee

IPC: G06N3/08 ,  G11C11/54 ,  G06N3/04

Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

公开(公告)号：US20230267973A1

公开(公告)日：2023-08-24

申请号：US18074528

申请日：2022-12-05

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C7/1063

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

公开(公告)号：US20230153375A1

公开(公告)日：2023-05-18

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20220413801A1

公开(公告)日：2022-12-29

申请号：US17679090

申请日：2022-02-24

Applicant: Industrial Technology Research Institute

Inventor： Jian-Wei Su ,  Chih-Sheng Lin ,  Peng-I Mei ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jheng Yang Dai

IPC: G06F7/523 ,  G06F7/50

Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.

公开(公告)号：US12142342B2

公开(公告)日：2024-11-12

申请号：US18074528

申请日：2022-12-05

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

公开(公告)号：US11599600B2

公开(公告)日：2023-03-07

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

公开(公告)号：US11423983B2

公开(公告)日：2022-08-23

申请号：US17322509

申请日：2021-05-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-Sheng Lin ,  Sih-Han Li ,  Yu-Hui Lin ,  Jian-Wei Su

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/06

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values. The comparator compares the accumulated data weight value with the reference value(s) to generate a data weight state.