公开(公告)号：US20240220210A1

公开(公告)日：2024-07-04

申请号：US18152170

申请日：2023-01-10

Applicant: Industrial Technology Research Institute

Inventor： Chia-Hsiang Yang ,  Liang-Hsin Lin ,  Yu-Ling Kang ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G06F7/72 ,  G06F5/01

CPC classification number: G06F7/729 ,  G06F5/01

Abstract: A modulo divider and a modulo division operation method for binary data are provided, including: converting a first variant and a second variant to a variant set according to a first mapping table; generating a fifth variant and a sixth variant according to the variant set; generating a seventh variant and an eighth variant according to the variant set; updating the first variant according to one of the fifth variant and the sixth variant and updating the second variant according to the other one of the fifth variant and the sixth variant; updating the third variant according to one of the seventh variant and the eighth variant and updating the fourth variant according to the other one of the seventh variant and the eighth variant; and outputting the third variant as a result of a modulo division operation in response to determining the updating of the third variant being finished.

公开(公告)号：US12142342B2

公开(公告)日：2024-11-12

申请号：US18074528

申请日：2022-12-05

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

公开(公告)号：US11599600B2

公开(公告)日：2023-03-07

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

公开(公告)号：US11423983B2

公开(公告)日：2022-08-23

申请号：US17322509

申请日：2021-05-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-Sheng Lin ,  Sih-Han Li ,  Yu-Hui Lin ,  Jian-Wei Su

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/06

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values. The comparator compares the accumulated data weight value with the reference value(s) to generate a data weight state.

公开(公告)号：US20230267973A1

公开(公告)日：2023-08-24

申请号：US18074528

申请日：2022-12-05

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C7/1063

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

公开(公告)号：US20230153375A1

公开(公告)日：2023-05-18

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20140172282A1

公开(公告)日：2014-06-19

申请号：US13831743

申请日：2013-03-15

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Shih-An Feng ,  Yi-Chun Lin ,  Yu-Hui Lin ,  Syuan-Yi Chen ,  Chun-Che Chang

IPC: G06F17/00

CPC classification number: B60L58/12 ,  B60L53/60 ,  B60L2240/622 ,  B60L2240/68 ,  B60L2240/70 ,  B60L2240/72 ,  B60L2250/12 ,  B60L2250/14 ,  B60L2250/16 ,  B60L2260/52 ,  B60L2260/54 ,  B60L2260/58 ,  Y02T10/7005 ,  Y02T10/7044 ,  Y02T10/705 ,  Y02T10/7072 ,  Y02T10/7291 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/162 ,  Y02T90/163

Abstract: A method and module for estimating after-charge drivable range of an electric vehicle and a driving assistant device are provided. The method includes a power supplement location selecting step, a planned charging time determining step, an after-charge total power estimating step, and an after-charge drivable range estimating step. The planned charging time determining step calculates an estimated driving time for arriving at each power supplement location and an estimated charge waiting time, and determines a planned charging time at each power supplement location. The after-charge total power estimating step calculates an estimated power increment of the electric vehicle and an estimated after-charge total power. The after-charge drivable range estimating step calculates an estimated after-charge drivable range of the electric vehicle centering at each power supplement location according to the current driving information and each estimated after-charge total power.

Abstract translation: 提供一种用于估计电动车辆和驾驶辅助装置的后充电可驱动范围的方法和模块。 该方法包括功率补充位置选择步骤，计划充电时间确定步骤，后充电总功率估计步骤和后充电可驱动范围估计步骤。 计划充电时间确定步骤计算用于到达每个功率补充位置的估计驱动时间和估计的充电等待时间，并且确定每个功率补充位置处的计划充电时间。 后充电总功率估计步骤计算电动车辆的估计功率增量和估计的后充电总功率。 后充电驱动范围估计步骤根据当前驾驶信息和每个估计的后充电总功率计算以每个功率补充位置为中心的电动车辆的估计的充电后可驱动范围。

公开(公告)号：US11741189B2

公开(公告)日：2023-08-29

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20210397675A1

公开(公告)日：2021-12-23

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.