公开(公告)号：US20160043302A1

公开(公告)日：2016-02-11

申请号：US14887168

申请日：2015-10-19

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Charles C. KUO ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Uday SHAH

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.

Abstract translation: 具有用于施加电场的场板的旋转转矩存储器（STTM）装置，以减少传递转矩感应磁化切换所需的临界电流。 实施例不仅利用电流感应磁场或自旋转移转矩，还利用电场诱导的磁偶极取向的操纵来设置磁性器件元件中的状态（例如，写入存储元件）。 由MTJ电极和场板之间的电压差产生的电场向磁性隧道结（MTJ）的自由磁性层施加电场，以在至少一部分自由磁性层上调制一个或多个磁性能 。

公开(公告)号：US20160365385A1

公开(公告)日：2016-12-15

申请号：US15247710

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： Ravi PILLARISETTY ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  David L. KENCKE ,  Uday SHAH ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US20180226478A1

公开(公告)日：2018-08-09

申请号：US15747719

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Uygar E. AVCI ,  David L. KENCKE ,  Patrick MORROW ,  Kerryann FOLEY ,  Stephen M. CEA ,  Rishabh MEHANDRU

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.