公开(公告)号：US20240220420A1

公开(公告)日：2024-07-04

申请号：US18148994

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Chunhui Mei ,  Doddaballapur Jayasimha ,  Aravindh V. Anantaraman ,  Yongsheng Liu ,  Hong Jiang

IPC: G06F12/121 ,  G06F12/0895

CPC classification number: G06F12/121 ,  G06F12/0895

Abstract: Locally biased cache replacement for a clustered cache architecture is described. An example of an apparatus includes clusters of cores; a clustered cache including multiple cache partitions for the clusters of cores, each cache partition including multiple cachelines; and a computer memory including memory partitions, each of the cache partitions being associated with a respective local memory partition, wherein each cacheline of the cache partitions includes a cacheline tag, each cacheline tag including a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed; and wherein the clustered cache includes circuitry to select cachelines for cache replacement in a cache partition based on values of the tags of the cachelines.

公开(公告)号：US12032500B2

公开(公告)日：2024-07-09

申请号：US17022212

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Ajit Krisshna Nandyal Lakshman ,  Doddaballapur Jayasimha

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4282 ,  G06F2213/0026

Abstract: In one embodiment, a fabric circuit is to receive requests for ownership and data commits from an agent. The fabric circuit includes a control circuit to maintain statistics regarding the requests for ownership and the data commits and throttle the fabric circuit based at least in part on the statistics. Other embodiments are described and claimed.

公开(公告)号：US20240211258A1

公开(公告)日：2024-06-27

申请号：US18145770

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Yuvraj Dhillon ,  Doddaballapur Jayasimha ,  Aravindh V. Anantaraman ,  Yongsheng Liu

IPC: G06F9/30 ,  G06F11/34 ,  G06F12/02

CPC classification number: G06F9/30047 ,  G06F9/30189 ,  G06F11/3409 ,  G06F12/0246

Abstract: Remote atomics for clustered processing operations are described. An example of a graphics processor includes a clustered processing architecture including multiple clusters and one or more memory elements, including a first memory element containing a home agent, the apparatus to receive, at a first caching agent for a first cluster, a request for performance of an atomic operation requiring a data stored in a cacheline at a memory address associated with the home agent; evaluate one or more factors including a current ownership of the memory address; and, based at least in part on the factors, determine whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent for performance of the atomic operation.

公开(公告)号：US12177277B2

公开(公告)日：2024-12-24

申请号：US17313353

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Lokpraveen Mosur ,  Ilango Ganga ,  Robert Cone ,  Kshitij Arun Doshi ,  John J. Browne ,  Mark Debbage ,  Stephen Doyle ,  Patrick Fleming ,  Doddaballapur Jayasimha

IPC: H04L65/61 ,  H04L47/50 ,  H04L49/9005

Abstract: In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.

公开(公告)号：US20210406056A1

公开(公告)日：2021-12-30

申请号：US16912788

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Doddaballapur Jayasimha ,  Raghu Ram Kondapalli

IPC: G06F9/455 ,  G06F9/50 ,  G06F12/0873 ,  G06F12/1045

Abstract: A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

公开(公告)号：US11567791B2

公开(公告)日：2023-01-31

申请号：US16912788

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Doddaballapur Jayasimha ,  Raghu Ram Kondapalli

IPC: G06F9/455 ,  G06F9/46 ,  G06F9/50 ,  G06F12/0873 ,  G06F12/1045

Abstract: A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

公开(公告)号：US09798556B2

公开(公告)日：2017-10-24

申请号：US14981388

申请日：2015-12-28

Applicant: INTEL CORPORATION

Inventor： Mani Ayyar ,  Eric Richard Delano ,  Ioannis Y. Schoinas ,  Akhilesh Kumar ,  Doddaballapur Jayasimha ,  Jose A. Vargas

IPC: G06F9/445 ,  G06F13/00 ,  G06F9/50 ,  G06F13/40 ,  G06F13/24

CPC classification number: G06F9/44505 ,  G06F9/50 ,  G06F9/5011 ,  G06F13/00 ,  G06F13/24 ,  G06F13/4081 ,  G06F13/409

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.